Method for manufacturing a contact structure used to electrically connect a semiconductor device

Patent metadata

Field	Value
Publication number	US-9349639-B2
Application number	US-201414510100-A
Country	US
Kind code	B2
Filing date	Oct 8, 2014
Priority date	Oct 8, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

First claim

What is claimed is:

1. A method for manufacturing contact structure electrically connecting a semiconductor device, the method comprising:
providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device comprises a gate structure and a source/drain region;
forming a patterned mask layer with a stripe hole on the substrate, wherein the stripe hole is disposed directly above the source/drain region;
forming a stripe-shaped mask layer on the substrate during the step of forming the patterned mask layer, wherein the stripe-shaped mask layer is spaced apart from the source/drain region and the patterned mask layer, and the stripe-shaped mask layer has the shape of stripe when viewed from a top down perspective;
forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed directly above the source/drain region and wherein the longest side of each of the slot holes is parallel to the longest side of the stripe hole, and a width of the stripe hole is greater than a width of each slot hole; and
forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, wherein the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

2. The method of claim 1 , wherein the patterned mask layer is made of a titanium nitride.

3. The method of claim 1 , wherein the patterned photoresist layer has a multi-layered structure.

4. The method of claim 1 , wherein at least one of the slot holes is disposed directly above the stripe hole.

5. The method of claim 1 , wherein the step of forming the patterned mask layer comprises:
depositing a mask layer on the interlayer dielectric; and
patterning the mask layer to thereby form the patterned mask layer.

6. The method of claim 5 , wherein the step of forming the patterned photoresist layer comprises:
coating a photoresist layer on the patterned mask layer; and
patterning the photoresist layer to thereby form the patterned photoresist layer.

7. The method of claim 1 , wherein the patterned mask layer is partially exposed from the bottom of the slot holes after the step of forming the patterned photoresist layer.

8. The method of claim 1 , further comprising filling a conductive material into the contact hole.

9. The method of claim 8 , further comprising removing the patterned mask layer before the step of filling the conductive material into the contact hole.

10. The method of claim 1 , further comprising removing the patterned mask layer after the step of forming the contact hole.

11. The method of claim 1 , further comprising depositing another interlayer dielectric on the gate structure before the step of forming the stripe-shaped mask layer.

12. The method of claim 11 , wherein the interlayer dielectric disposed on the gate structure is interposed between the gate structure and the stripe-shaped mask layer.

13. The method of claim 1 , wherein at least one of the slot holes is laterally spaced apart from the patterned mask layer when the step of forming the patterned photoresist layer is completed.

14. A method for manufacturing contact structure electrically connecting a semiconductor device, the method comprising:
providing a substrate having an interlayer dielectric thereon;
forming a mask layer on the interlayer dielectric;
patterning the mask layer so as to concurrently form a patterned mask layer and a stripe-shaped mask layer, wherein the patterned mask layer comprises a stripe hole and is laterally spaced apart from the stripe-shaped mask layer;
forming a patterned photoresist layer having a plurality of slot holes on the patterned mask layer and the stripe-shaped mask layer, wherein the longest side of at least one of the slot holes is parallel to the longest side of the stripe hole and laterally spaced apart from the pattern mask layer, and at least another one of the slot holes crosses over the stripe-shaped mask layer; and
etching the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask so as to form a plurality of contact holes in the interlayer dielectric.

15. The method of claim 14 , wherein the stripe-shaped mask layer has the shape of stripe when viewed from a top down perspective.

Assignees

• United Microelectronics Corp

Inventors

• Hung Ching-Wen
• Huang Chih-Sen

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title