Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability

Patent metadata

Field	Value
Publication number	US-9349632-B2
Application number	US-201514589432-A
Country	US
Kind code	B2
Filing date	Jan 5, 2015
Priority date	Mar 14, 2006
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A method of forming a trench isolation structure in an integrated circuit comprising:
forming a smaller isolation trench and a larger isolation trench in a semiconductor substrate, wherein said larger isolation trench has a greater width than said smaller isolation trench and the same depth as the smaller isolation trench;
forming an oxide layer over said substrate and on all surfaces of said smaller and larger isolation trenches;
forming a nitride layer over said oxide layer, said nitride layer completely filling said smaller isolation trench, but only lining said larger isolation trench;
removing a portion of said nitride layer to form a recess in said nitride layer in said smaller isolation trench and to completely remove said nitride layer lining for said larger isolation trench; and
forming a layer of high density plasma oxide over said substrate to fill said smaller and larger isolation trenches.

2. The method of claim 1 , wherein said nitride layer is removed such that an upper surface of said nitride layer in said smaller isolation trench is below an upper surface of said semiconductor substrate.

3. The method of claim 1 , further comprising the act of performing an oxide spacer etch on said oxide layer after removing said portion of said nitride layer to etch back said oxide layer, leaving an oxide liner in said smaller isolation trench and said large isolation trench.

4. The method of claim 1 , further comprising the act of planarizing said high density plasma oxide.

5. The memory device of claim 1 , further comprising forming a second nitride material directly above and proximate to said semiconductor material before forming said first and second trench isolation regions.

6. A method of forming a trench isolation structure in an integrated circuit comprising:
forming a first isolation trench and a second isolation trench in a semiconductor substrate, wherein said second isolation trench has a greater width than said first isolation trench and the same depth as the first isolation trench;
forming a nitride layer over said substrate such that said nitride layer completely fills said first isolation trench while only lining said second isolation trench;
removing a portion of said nitride layer to form a recess in said nitride layer in said first isolation trench; and
forming an insulating layer of material over said substrate to fill said first and second isolation trenches.

7. The method of claim 6 , wherein an upper surface of said nitride layer in said first isolation trench is below an upper surface of said semiconductor substrate.

8. The method of claim 6 , further comprising the act of forming an oxide layer over said substrate and on all surfaces of said first and second isolation trenches prior to said act of forming a nitride layer.

9. The method of claim 8 , further comprising the act of etching said oxide layer after removing said portion of said nitride layer to form an isolating liner in said first isolation trench and second isolation trench.

10. The method of claim 6 , wherein said insulating layer is an HDP oxide layer.

11. The method of claim 6 , further comprising the act of planarizing said insulating layer to an upper surface of said semiconductor substrate.

12. The method of claim 6 , further comprising forming a second nitride material directly above and proximate to said semiconductor material before forming said first and second isolation trenches.

Assignees

• Micron Technology Inc

Inventors

• Zhou Xianfeng

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title