High voltage switch, nonvolatile memory device comprising same, and related method of operation

Patent metadata

Field	Value
Publication number	US-9349457-B2
Application number	US-201414455344-A
Country	US
Kind code	B2
Filing date	Aug 8, 2014
Priority date	Nov 21, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch includes a PMOS transistor transmitting the second drive voltage to an output terminal according to a voltage applied to its gate, a first depletion mode transistor providing the second drive voltage to the PMOS transistor according to an output signal fed back from the output terminal, a second depletion mode transistor receiving the second drive voltage through one end and providing a switching voltage to another end according to a switching control signal, and a level shifter providing the switching voltage to a gate of the PMOS transistor according to an enable signal and a reverse enable signal.

First claim

What is claimed is:

1. A high voltage switch operating in response to a first drive voltage and a second drive voltage higher than the first drive voltage, comprising:
a positive metal oxide semiconductor (PMOS) transistor transmitting the second drive voltage to an output terminal according to a voltage applied to a gate of the PMOS transistor;
a first depletion mode transistor providing the second drive voltage to the PMOS transistor according to an output signal fed back from the output terminal;
a second depletion mode transistor receiving the second drive voltage through one end and providing a switching voltage to another end according to a switching control signal; and
a level shifter connected to receive the switching voltage output from the second depletion mode transistor, the level shifter providing the switching voltage to the gate of the PMOS transistor according to an enable signal and an inverted enable signal,
wherein the enable signal has a ground voltage or a level of the first drive voltage responsive to an input signal and a control signal.

2. The high voltage switch of claim 1 , wherein the first depletion mode transistor and the second depletion mode transistor have a same threshold voltage level.

3. The high voltage switch of claim 1 , further comprising a logic block generating the enable signal to control the level shifter responsive to the input signal and the control signal.

4. The high voltage switch of claim 3 , wherein the logic block transmits the switching control signal having a same level as the input signal to a gate of the second depletion mode transistor.

5. The high voltage switch of claim 1 , wherein the level shifter provides the switching voltage or the ground voltage to the gate of the PMOS transistor according to the enable signal and the inverted enable signal.

6. The high voltage switch of claim 1 , wherein where the enable signal has a high level and the inverted enable signal has a low level, the level shifter provides the switching voltage to the gate of the PMOS transistor.

7. The high voltage switch of claim 6 , wherein where the input signal has a low level, the switching voltage has a same value as a threshold voltage of the second depletion mode transistor.

8. The high voltage switch of claim 6 , wherein where the input signal has a high level, the switching voltage has a value which is a sum of a threshold voltage of the second depletion mode transistor and the first drive voltage.

9. The high voltage switch of claim 1 , wherein where the enable signal has a low level and the inverted enable signal has a high level, the level shifter provides the ground voltage to the gate of the PMOS transistor.

10. The high voltage switch of claim 1 , wherein where the input signal and the control signal have a low level, the level shifter provides a threshold voltage of the second depletion mode transistor to the gate of the PMOS transistor.

11. The high voltage switch of claim 1 , wherein where the input signal has a high level and the control signal has a low level, the level shifter provides the ground voltage to the gate of the PMOS transistor.

12. The high voltage switch of claim 1 , wherein where the input signal and the control signal have a high level, the level shifter provides a value that is a sum of a threshold voltage of the second depletion mode transistor and the first drive voltage to the gate of the PMOS transistor.

13. A nonvolatile memory device comprising:
a memory cell array comprising memory cells connected to a word line and a bit line;
a pass transistor transmitting a first high voltage to the word line; and
a high voltage switch boosting a level of an input signal to a level of a second high voltage to provide the boosted input signal to a gate of the pass transistor,
wherein the high voltage switch comprises:
a PMOS transistor transmitting the second high voltage to an output terminal according to a voltage applied to a gate of the PMOS transistor;
a first depletion mode transistor transmitting the second high voltage to the PMOS transistor according to an output signal fed back from the output terminal;
a second depletion mode transistor receiving the second high voltage through one end to provide a switching voltage to another end according to a switching control signal; and
a level shifter connected to receive the switching voltage output from the second depletion mode transistor, the level shifter providing the switching voltage to the gate of the PMOS transistor according to an enable signal and an inverted enable signal,
wherein the enable signal has a ground voltage or a level of a drive voltage responsive to an input signal and a control signal.

14. The nonvolatile memory device of claim 13 , wherein the first depletion mode transistor and the second depletion mode transistor have a same threshold voltage level.

15. The nonvolatile memory device of claim 13 , wherein the high voltage switch further comprises a logic block generating the enable signal for controlling the level shifter responsive to the input signal and the control signal.

16. A method of operating a non-volatile memory device comprising a high voltage switch that controls application of a high voltage signal to a memory array in response to a first drive signal and a second drive signal having a higher voltage level than the first drive signal, the method comprising:
operating a positive metal oxide semiconductor (PMOS) transistor to transmit the second drive voltage to an output terminal according to a voltage applied to a gate of the PMOS transistor;
operating a first depletion mode transistor to provide the second drive voltage to the PMOS transistor according to an output signal fed back from the output terminal;
operating a second depletion mode transistor to receive the second drive voltage through one end and to provide a switching voltage to another end according to a switching control signal; and
operating a level shifter to receive the switching voltage from the second depletion mode transistor, and to provide the switching voltage to the gate of the PMOS transistor according to an enable signal and an inverted a reverse enable signal,
wherein the enable signal has a ground voltage or a level of the first drive signal responsive to an input signal and a control signal.

17. The method of claim 16 , wherein the first depletion mode transistor and the second depletion mode transistor have a same threshold voltage level.

18. The method of claim 16 , further comprising operating a logic block to generate the enable signal to control the level shifter responsive to the input signal and the control signal.

19. The method of claim 18 , wherein the logic block transmits the switching control signal having a same level as the input signal to a gate of the second depletion mode transistor.

20. The method of claim 16 , wherein the level shifter provides the switching voltage or the ground voltage to the gate of the PMOS transistor responsive to the enable signal and the inverted enable signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Taehyun
• Min Youngsun

Classifications

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• H03K17/165

  by feedback from the output circuit to the control circuit · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title