Symmetric keying and chain of trust

US9348997B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9348997-B2
Application numberUS-201414543097-A
CountryUS
Kind codeB2
Filing dateNov 17, 2014
Priority dateMar 13, 2014
Publication dateMay 24, 2016
Grant dateMay 24, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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The present disclosure is directed to sealing data using chain of trust key derivation. In at least one embodiment, a chain of trust may be used to derive sealing keys for sealing data on a device. The device may comprise, for example, at least a memory and processor. The processor may be to at least load code modules from the memory. Following the loading of a code module, the processor may further be to measure the code module, determine a sealing key corresponding to the code module, wherein the sealing key is determined based at least on a prior sealing key corresponding to a previously loaded code module and the measurement of the code module, and seal data corresponding to the loaded code module using the sealing key. Since the sealing keys are state dependent, a method for authorized migration of sealed data during software upgrades is also disclosed.

First claim

Opening claim text (preview).

What is claimed: 1. A device configured for sealing data using a chain of trust, comprising: a memory; and a processor to at least load code modules from the memory, wherein following the loading of a selected code module the processor is further to: measure the selected code module; determine a sealing key corresponding to the selected code module, wherein the sealing key is determined based at least on a prior sealing key corresponding to a previously loaded code module and…

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What does patent US9348997B2 cover?
The present disclosure is directed to sealing data using chain of trust key derivation. In at least one embodiment, a chain of trust may be used to derive sealing keys for sealing data on a device. The device may comprise, for example, at least a memory and processor. The processor may be to at least load code modules from the memory. Following the loading of a code module, the processor may fu…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H04L9/0827. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 24 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).