Controlling prefetch aggressiveness based on thrash events

US9348753B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9348753-B2
Application numberUS-201213648733-A
CountryUS
Kind codeB2
Filing dateOct 10, 2012
Priority dateOct 10, 2012
Publication dateMay 24, 2016
Grant dateMay 24, 2016

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Abstract

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A method and apparatus for controlling the aggressiveness of a prefetcher based on thrash events is presented. An aggressiveness of a prefetcher for a cache is controlled based upon a number of thrashed cache lines that are replaced by a prefetched cache line and subsequently written back into the cache before the prefetched cache line has been accessed.

First claim

Opening claim text (preview).

What is claimed: 1. A method, comprising: identifying a number of thrashed cache lines, wherein each of the thrashed cache lines is a cache line that is both replaced by a prefetched cache line and subsequently written back into a cache before the prefetched cache line has been accessed; and controlling an aggressiveness of a prefetcher based on the identified number of thrashed cache lines. 2. The method of claim 1 , wherein controlling the aggressiveness…

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What does patent US9348753B2 cover?
A method and apparatus for controlling the aggressiveness of a prefetcher based on thrash events is presented. An aggressiveness of a prefetcher for a cache is controlled based upon a number of thrashed cache lines that are replaced by a prefetched cache line and subsequently written back into the cache before the prefetched cache line has been accessed.
Who is the assignee on this patent?
Advanced Micro Devices Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/0862. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 24 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).