Solid state memory command queue in hybrid device

Patent metadata

Field	Value
Publication number	US-9348747-B2
Application number	US-201314066266-A
Country	US
Kind code	B2
Filing date	Oct 29, 2013
Priority date	Oct 29, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

Systems and methods are disclosed for improving performance in of storage device latency. In an embodiment, an apparatus may comprise a controller configured to receive a first data access command at a device including a nonvolatile solid state memory and a disc memory, and when the first data access command is directed to the nonvolatile solid state memory, store the first data access command to a first command queue for the nonvolatile solid state memory. In another embodiment, a method may comprise receiving, at a data storage device, a first data access command, storing the first data access command in a first command queue, determining whether the data access command is directed to a Flash memory or a disc memory, and storing the first data access command in a second command queue when the first data access command is directed to the Flash memory.

First claim

What is claimed is:

1. An apparatus comprising:
a data storage
device including:
a first nonvolatile solid state memory;
a second nonvolatile memory having a slower access speed than the first nonvolatile solid state memory;
a first command queue configured to receive all data access commands from a host device;
a second command queue configured to store commands directed to the first nonvolatile solid state memory;
a first controller configured to:
receive a first data access command from the first command queue;
determine which of the first nonvolatile solid state memory and the second nonvolatile memory the first data access command is directed to;
when the first data access command is directed to the first nonvolatile solid state memory, store the first data access command to the second command queue;

a solid state memory controller configured to receive the first data access command from the second command queue and execute the first data access command to access the first nonvolatile solid state memory; and
the second command queue interposed between the first controller and the solid state memory controller and configured to intercept data access commands directed to the solid state memory controller.

2. The apparatus of claim 1 further comprising:
the first controller further configured to:
after storing the first data access command to the second command queue, send an indication that the first data access command has been received and that additional commands may be sent to the first controller.

3. The apparatus of claim 1 further comprising:
the first controller further configured to:
receive a second data access command directed to the first nonvolatile solid state memory before execution of the first data access command has completed; and
store the second data access command to the second command queue.

4. The apparatus of claim 3 further comprising:
the first controller further configured to:
store a third data access command to the second command queue;

the solid state memory controller further configured to:
determine if both the second data access command and the third data access command can be performed with a single data access; and
perform the single data access based on the determination.

5. The apparatus of claim 1 further comprising:
an interface configured to receive commands from the host device; and
the first controller further configured to return results of commands to the host device over the interface.

6. The apparatus of claim 1 further comprising:
the first nonvolatile solid state memory is a NAND Flash memory; and
the second nonvolatile memory is a disc memory.

7. The apparatus of claim 1 further comprising:
a data access command is directed to the first nonvolatile solid state memory when the data access command requests data stored in the first nonvolatile solid state memory or when the data access command includes data to be written to the first nonvolatile solid state memory.

8. The apparatus of claim 1 further comprising:
the solid state memory controller further configured to perform a plurality of read or write data access operations stored in the second command queue on the first nonvolatile solid state memory based on a priority value associated with each of the plurality of data access operations.

9. The apparatus of claim 1 further comprising:
the first command queue and the second command queue include volatile random access memory; and
the second command queue is physically separate from the solid state memory controller.

Assignees

• Seagate Technology Llc

Inventors

• Keeler Stanton Macdonough
• Lapanse Margot Ann

Classifications

• G06F12/0873

  Mapping of cache memory to specific storage devices or parts thereof · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/217

  Hybrid disk, e.g. using both magnetic and solid state storage devices · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title