Smart bridge for memory core
US-9218852-B2 · Dec 22, 2015 · US
Data accessing method for flash memory module
US9348693B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9348693-B2 |
| Application number | US-201313901239-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 23, 2013 |
| Priority date | Feb 21, 2008 |
| Publication date | May 24, 2016 |
| Grant date | May 24, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet.
First claim
Opening claim text (preview).
What is claimed is: 1. A data accessing method, suitable for a flash memory module, and the data accessing method comprising: performing an error correction encoding for a data packet to be stored in the flash memory module to generate a sequence data code containing the data packet and a corresponding error correction code of the data packet, wherein the data packet comprises user data and system data, and the system data comprises logical to physical mapping relationship of the…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
- G06F11/1068Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9348693B2 cover?
- A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error corr…
- Who is the assignee on this patent?
- Phison Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1068. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 24 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).