Apparatus and method for repairing cache arrays in a multi-core microprocessor
US-2015339232-A1 · Nov 26, 2015 · US
Correctable configuration data compression and decompression system
US9348690B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9348690-B2 |
| Application number | US-201313972812-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 21, 2013 |
| Priority date | Aug 21, 2013 |
| Publication date | May 24, 2016 |
| Grant date | May 24, 2016 |
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Abstract
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An apparatus has a shared fuse array and a plurality of x86-compatible microprocessors disposed on a die. The shared fuse array has a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes accessible by a plurality of x86-compatible microprocessors and another plurality of semiconductor fuses programmed with uncompressed system hardware configuration data that is employed to initialize control circuit elements within the plurality of x86-compatible microprocessors. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessors is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of microprocessors. The each of the plurality of microprocessors includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors in said compressed configuration data resulting in corrected compressed configuration data, to decompress the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements.
First claim
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What is claimed is: 1. An apparatus for storing and decompressing configuration data in a multi-core microprocessor, the apparatus comprising: a shared fuse array, disposed on a die, said shared fuse array comprising: a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes accessible by a plurality of x86-compatible microprocessors; and another plurality of semiconductor fuses programmed with uncompressed sy…
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- What does patent US9348690B2 cover?
- An apparatus has a shared fuse array and a plurality of x86-compatible microprocessors disposed on a die. The shared fuse array has a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes accessible by a plurality of x86-compatible microprocessors and another plurality of semiconductor fuses programmed with uncompressed syst…
- Who is the assignee on this patent?
- Via Tech Inc, Via Alliance Semiconductor Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F11/10. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 24 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).