Computer system

Patent metadata

Field	Value
Publication number	US-9348628-B2
Application number	US-201313845864-A
Country	US
Kind code	B2
Filing date	Mar 18, 2013
Priority date	Jul 13, 2009
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.

First claim

What is claimed is:

1. A computer system comprising:
a physical computer including one or more physical processors;
a virtual machine monitor; and
a virtual machine including one or more virtual processors such that the physical processors are time-shared among the virtual processors by the virtual machine monitor,
wherein the virtual machine monitor:
manages, for each of the virtual processors, a difference between a virtual processor halt exit time (ts) and a virtual processor halt start time (TS) as a virtual processor halt duration (X) where ts indicates a time to exit a halt state of a processor state (VS) of the respective virtual processor and TS indicates a time to start waiting to exit the halt state of the processor status of the respective virtual processor,
calculates a virtual processor halt duration predicted value (E), which is an average of N previous virtual processor halt durations X of the virtual processors, where N is an integer greater than one,
when receiving a halt request for one of the virtual processors running on one of the physical processors, changes the processor state from an execution state to the halt state,
compares the virtual processor halt duration predicted value E with a blocking processing time cost (TB),
when E<TB, makes a schedule state (SS) of the one of the virtual processors a run state in which the one of the physical processors assigned to the one of the virtual processors is not released and waits for the one of the virtual processors to exit from the halt state, and
when E>=TB, makes the schedule state (SS) of the one of the virtual processors a block state in which the one of the physical processors assigned to the one of the virtual processors is released and waits for the one of the virtual processors to exit from the halt state.

2. The computer system according to claim 1 ,
wherein the virtual machine monitor:
enables execution of a program on the one of the virtual processors if the one of the virtual processors is in the execution state, and
disables execution of the program on the one of the virtual processors if the one of the virtual processors is in the halt state.

3. The computer system according to claim 1 ,
wherein the one of the virtual processors:
continues running on the one of the physical processors if the schedule state is the run state, and
stops running on the one of the physical processors if the schedule state is the block state.

4. The computer system according to claim 1 ,
wherein TB is a processing time in case of selecting a blocking method which waits for the exit of the halt state of the processor state when the schedule state is the block state and the virtual processor is woken immediately without any wait time.

5. The computer system according to claim 4 ,
wherein, when E<TB, the virtual machine monitor:
selects a busy wait method which waits for the exit of the halt state of the processor state when the schedule state is the run state,
calculates a busy wait execution time which is a difference between a current system time and TS,
compares the busy wait execution time with a busy wait execution time threshold (TH),
continues the busy wait method when the busy wait execution time<TH, and
switches from the busy wait method to the blocking method when the busy wait execution time>=TH.

6. The computer system according to claim 4 ,
wherein, when E>=TB and selecting the method of waiting for the exit of the halt state of the processor state, the virtual machine monitor:
determines whether there is another of the virtual processors to be assigned to the one of the physical processors,
selects the blocking method if there is another of the virtual processors to be assigned to the one of the physical processors,
compares, if there are no other virtual processors to be assigned to the one of the physical processors, the virtual processor halt duration predicted time E with the busy wait execution time threshold TH,
when E>=TH, selects the blocking method,
when E<TH, compares a virtual processor halt exit time predicted value (F) with a predicted value (F′), where the virtual processor halt exit time predicted value F is a sum of TS and E and the predicted value F′ is a top value managed in a management queue for managing a plurality of the virtual processor halt exit time predicted values F,
when F>=F′, selects the busy wait method, and
when F<F′, selects the blocking method.

7. The computer system according to claim 5 ,
wherein the virtual machine monitor, which selected the busy wait method:
when receiving the halt exit request for the one of the virtual processors, changes the processor state from the halt state to the execution state, and resumes the execution of the program on the one of the virtual processors in which the schedule state continues to be the run state.

8. The computer system according to claim 6 ,
wherein the virtual machine monitor, which selected the busy wait method:
when receiving the halt exit request for the one of the virtual processors, changes the processor state from the halt state to the execution state, and resumes the execution of the program on the one of the virtual processor in which the schedule state continues to be the run state.

9. The computer system according to claim 6 ,
wherein the virtual machine monitor, which selected the blocking method:
blocks assignment of the halted one of the virtual processors to the one of the physical processors,
yields the one of the physical processors,
when receiving the halt exit request for the one of the virtual processors, changes the schedule state from the block state to a ready state, which enables to assign the one of the virtual processors to the physical processors,
re-allocates the one of the virtual processors in which schedule state is the ready state to the yielded one of the physical processors, and
resumes the execution of the program on the one of the virtual processors to which the yielded one of the physical processors is re-allocated.

Assignees

• Hitachi Ltd

Inventors

• Matsumoto Shuhei
• Inoue Hironori
• Wada Shintaro

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• Y02B60/144

  Cross-Sectional Technologies · mapped topic

• G06F9/45541

  Bare-metal, i.e. hypervisor runs directly on hardware · CPC title

• G06F2209/483

  Multiproc · CPC title

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title