Stitchable global clock for 3D chips

Patent metadata

Field	Value
Publication number	US-9348357-B2
Application number	US-201414318951-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A stitchable clock mesh, a dual operation mode method, and a master clock stratum are provided for a 3D chip stack. The stitchable clock mesh includes at least one clock mesh, on each of the two or more strata, having a plurality of sectors for providing a global clock signal. The stitchable clock mesh further includes mesh data sensors, on each of the two or more strata, for collecting mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The stitchable clock mesh further includes mesh segmentation and joining circuitry for selectively performing a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.

First claim

What is claimed is:

1. A stitchable clock mesh for a 3D chip stack having two or more strata, comprising:
at least one clock mesh, on each of the two or more strata, having a plurality of sectors for providing a global clock signal to various chip locations;
mesh data sensors, on each of the two or more strata, for collecting mesh data for the at least one mesh, the mesh data including measured functional data and measured performance data for a current system configuration; and
mesh segmentation and joining circuitry for selectively performing a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.

2. The stitchable clock mesh of claim 1 , wherein the segmentation operation segments at least a portion of the at least one clock mesh into two or more smaller clock mesh regions.

3. The stitchable clock mesh of claim 1 , wherein the joining operation joins at least two smaller clock mesh regions into one or more larger clock mesh regions.

4. The stitchable clock mesh of claim 1 , wherein the segmentation operation is performed to drive one or more specific macros for the at least one smaller clock mesh region.

5. The stitchable clock mesh of claim 1 , wherein the segmentation operation is performed to shut down power to one or more chip components.

6. The stitchable clock mesh of claim 1 , wherein at least one of the segmentation operation and the joining operation are iteratively repeated until an optimal system configuration is reached from among the plurality of system target configurations responsive to an evaluation of the mesh data.

7. The stitchable clock mesh of claim 1 , wherein the joining operation is performed to power up one or more chip components.

8. The stitchable clock mesh of claim 1 , wherein at least one of the segmentation operation and the joining operation are performed for thermal management.

9. The stitchable clock mesh of claim 1 , wherein mesh segmentation and joining circuitry comprises multiplexed clock buffers.

10. The stitchable clock mesh of claim 1 , wherein the mesh data comprises component functions, a process corner, and performance metrics therefor.

11. The stitchable clock mesh of claim 1 , wherein the at least one mesh or a portion thereof on each of the two or more strata is selectively controlled by a clock controller to operate independently of each other without synchronization there between in a first mode of operation and to operate in synchronization with each other in a second mode of operation.

12. A method for providing a dual operation mode in 3D chip stack having two or more strata, the method comprising:
providing an independent operation mode, wherein each of the two or more strata operate independently and without inter-strata synchronous communication there between;
providing an integrated operation mode with inter-strata communication between the two or more strata through inter-strata interconnects; and
providing a controller for selectively enabling any of the independent operation mode and the integrated operation mode.

13. The method of claim 12 , wherein in the independent operation mode, the two or more strata have independent optimization for power savings.

14. The method of claim 12 , wherein in the independent operation mode, power supply and ground connections are shared between the two or more strata.

15. The method of claim 12 , wherein in the independent operation mode, at least a specific strata frequency and specific strata skew are optimized for each of the two or more strata.

16. The method of claim 12 , wherein in the integrated operation mode, power supply connections, ground connections, and one or more frequencies are shared between the two or more strata with global clock alignment across the two or more strata.

17. The method of claim 12 , wherein in the integrated operation mode, resource sharing is enabled between the two or more strata.

18. The method of claim 12 , further comprising selecting a clock source, for use on a given one of the two or more strata, from a same one of the two or more strata or an adjacent one of the two or more strata.

19. A master clock stratum for a 3D chip stack including two or more strata, the master clock stratum comprising:
a power supply portion for providing power supplying connections;
a clock portion for providing clock supplying connections;
pervasive components for performing pervasive chip functions; and
a controller for selectively providing, to other ones of the two or more strata, at least one of the power supplying connections, clock supplying connections, and the pervasive chip functions.

20. The master clock stratum of claim 19 , wherein said controller selectively enables inter-strata pathways through inter-strata connections to selectively provide the at least one of the power supplying connections, clock supplying connections, and the pervasive chip functions.

Assignees

• IBM

Inventors

• Franch Robert L
• Kursun Eren
• Pang Liang-Teck
• Restle Phillip J

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/32

  Means for saving power · CPC title

• G06F1/206

  comprising thermal management · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title