Splice chips for optical fiber splice cassettes

Patent metadata

Field	Value
Publication number	US-9348105-B2
Application number	US-201313901112-A
Country	US
Kind code	B2
Filing date	May 23, 2013
Priority date	May 25, 2012
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A splice chip includes a base, separation members extending upwardly from the base to define a plurality of rows, and latching fingers extending upwardly from the base to further define the rows. At least one of the rows includes at least a first latching finger, a second latching finger, and a third latching finger. The third latching finger is shorter than the first and second latching fingers. The second latching finger is shorter than the first latching finger. The row also may include a fourth latching finger that is the same height as the first latching finger.

First claim

The invention claimed is:

1. A splice chip comprising:
a base having a first side, an opposite second side, and guide edges along part of a perimeter of the base;
a plurality of separation members extending upwardly from the base to define a plurality of rows, each row including two separation members;
a plurality of latching fingers extending upwardly from the base to further define the rows, at least one of the rows including at least a first latching finger, a second latching finger, and a third latching finger, the third latching finger being shorter than the first and second latching fingers, and the second latching finger being shorter than the first latching finger, the first, second, and third latching fingers of the at least one row being disposed between the respective two separation members.

2. The splice chip of claim 1 , wherein the at least one row also includes a fourth latching finger that is the same height as the first latching finger.

3. The splice chip of claim 2 , wherein the second latching finger is disposed between the first latching finger and one of the separation members of said row; and wherein the third latching finger is disposed between the fourth latching finger and one of the separation members of said row.

4. The splice chip of any of claim 1 , wherein each row has the same arrangement of latching fingers.

5. The splice chip of any of claim 1 , further comprising a support wall disposed at one end of the base.

6. The splice chip of claim 5 , wherein the latching fingers all face towards the support wall.

7. The splice chip of any of claim 1 , wherein the third latching finger is sized to retain a first splice to the base.

8. The splice chip of claim 7 , wherein the second latching finger is sized to retain a second splice stacked on the first splice.

9. The splice chip of claim 8 , wherein the first and fourth latching fingers are sized to retain a third splice stacked on the second splice.

10. The splice chip of any of claim 1 , wherein the guide edges define opposite ends of the base.

11. A method of organizing fusion splices between a plurality of first optical fibers and a plurality of second optical fibers, the method comprising:
seating a first splice in a first row of a splice chip and latching the first splice to the splice chip with at least a first latching finger, the first row extending across a width of the splice chip, the width being about 1.2 inches to about 1.8 inches, wherein the first splice protects a fusion splice between one of the first optical fibers and one of the second optical fibers;
seating a second splice in the first row of the splice chip and latching the second splice to the splice chip with at least a second latching finger, wherein the second splice protects a fusion splice between another of the first optical fibers and another of the second optical fibers, the second latching finger being laterally aligned with the first latching finger; and
seating a third splice in the first row of the splice chip and latching the third splice to the splice chip with at least a third latching finger, wherein the third splice protects a fusion splice between yet another of the first optical fibers and yet another of the second optical fibers, the third latching finger being laterally aligned with the first and second latching fingers.

12. The method of claim 11 , wherein latching the third splice to the splice chip comprises latching the third splice to the splice chip using the third latching finger and a fourth latching finger that is a common height with the third latching finger, the fourth latching finger being laterally aligned with the third latching finger.

13. The method of claim 11 , wherein latching the first splice to the splice chip with at least the first latching finger comprises latching the first splice to the splice chip with only the first latching finger.

14. The method of claim 11 , wherein seating each of the splices in the first row comprises sliding the splice between longitudinally spaced separation members.

15. The method of claim 11 , further comprising seating a fourth splice in a second row of the splice chip and latching the fourth splice to the splice chip with at least a fifth latching finger, wherein the fifth splice protects a fusion splice between one of the first optical fibers and one of the second optical fibers.

16. The method of claim 15 , wherein the fifth latching finger is aligned with the first latching finger of the first row and offset from the other latching fingers of the first row.

17. The method of claim 15 , wherein the fourth splice is seated in the second row before the second splice is seated in the first row.

18. A splice chip comprising:
a base defining a plurality of channels extending across a width of the base between first and second edges of the base, the base having a length extending between first and second ends of the base, the first and second ends extending between the first and second edges;
a support wall extending upwardly from the base at the first end of the base;
a plurality of first separation members extending upwardly from the base at the first edge of the base, each of the first separation members corresponding to a respective one of the channels, each first separation member defining a flat surface facing the first end of the base and a flat surface facing the second end of the base, each flat surface extending along a full height of the respective first separation member;
a plurality of second separation members extending upwardly from the base at the second edge of the base, each of the second separation members being laterally aligned with one of the first separation members, each second separation member defining a flat surface facing the first end of the base and a flat surface facing the second end of the base, each flat surface extending along a full height of the respective second separation member; and
a plurality of latching fingers extending upwardly from the base, each of the latching fingers corresponding with a respective one of the channels, each of the latching fingers including a hook extending outwardly over the respective channel towards the support wall, and each of the latching members being disposed between and laterally aligned with one of the first separation members and one of the second separation members.

19. The splice chip of claim 18 , wherein the latching fingers each have one of a plurality of heights, and wherein each channel corresponds with no more than one latching finger of each height.

Assignees

• Adc Telecommunications Inc
• Commscope Technologies Llc

Inventors

• Rudenick Paula
• Sievers Scott C
• Bran De León Oscar Fernando
• Cano Gustavo
• Saucedo Raul Mario

Classifications

• G02B6/44526

  Panels or rackmounts covering a whole width of the frame or rack · CPC title

• G02B6/4454 Primary

  with splices · CPC title

• G02B6/4452

  Distribution frames · CPC title

• G02B6/444

  Systems or boxes with surplus lengths · CPC title