Semiconductor device
US-2024421048-A1 · Dec 19, 2024 · US
Chip and circuit structure
US9345124B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9345124-B2 |
| Application number | US-201314235811-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 7, 2013 |
| Priority date | Oct 25, 2013 |
| Publication date | May 17, 2016 |
| Grant date | May 17, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
The present invention provides a chip structure and a circuit structure, chip structure is disposed on a printed circuit board provided with an element layer and a copper grounding layer, and comprises: a chip body disposed on the element layer and having a plurality of power pins; a power line disposed on the element layer for supplying electric power to the chip body; a plurality of power input lines, each of which has a body disposed on the copper grounding layer and two ends disposed on the element layer and connected with the body through corresponding through holes of the printed circuit board; and a plurality of bypass capacitors having one end connected with the power pins of the chip body through the element layer and the other end of the bypass capacitors connected with the power line through the power input line. The present invention further provides a chip structure. The power line of the chip structure and the circuit structure of the present invention is disposed on the element layer, so that the heat dissipation effect of the copper grounding layer is better, and the yield of the chip and corresponding circuit structure is improved.
First claim
Opening claim text (preview).
What is claimed is: 1. A chip structure, disposed on a printed circuit board provided with an element layer and a copper grounding layer, comprising: a chip body disposed on the element layer and having a plurality of power pins; a power line disposed on the element layer for supplying electric power to the chip body; a plurality of power input lines, each of which has a body disposed on the copper grounding layer, wherein two ends of the power input line are disposed on the e…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10W72/00Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9345124B2 cover?
- The present invention provides a chip structure and a circuit structure, chip structure is disposed on a printed circuit board provided with an element layer and a copper grounding layer, and comprises: a chip body disposed on the element layer and having a plurality of power pins; a power line disposed on the element layer for supplying electric power to the chip body; a plurality of power inp…
- Who is the assignee on this patent?
- Shenzhen China Star Optoelect
- What technology area does this patent fall under?
- Primary CPC classification H10W72/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 17 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).