Semiconductor integrated circuit and operation method of the same

Patent metadata

Field	Value
Publication number	US-9343950-B2
Application number	US-201314077262-A
Country	US
Kind code	B2
Filing date	Nov 12, 2013
Priority date	Nov 28, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

The present invention is to reduce the possibility that a DC-DC converter stops in the case where supply power is small and load current is large. Output terminals use a DC output voltage of a DC-DC converter so that an external battery can be charged or power can be supplied to a power-reception-side system on the outside, and a current limiting circuit limits load current of a power supply switch transistor flowing from a converter output terminal to the output terminals. An input voltage detecting circuit detects level of a DC input voltage of an input terminal, generates a detection signal, and supplies the detection signal to the current limiting circuit. In the case where the DC input voltage of the input terminal is at the low level, the current limiting circuit controls the maximum current by current limitation of the power supply switch transistor to a small current.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
an input terminal;
a DC-DC converter;
an output terminal;
a power supply switch transistor;
a current limiting circuit; and
an input voltage detecting circuit,
wherein a DC input voltage generated by rectifying and smoothing an RF reception signal can be supplied to the input terminal,
wherein the DC-DC converter can generate, from a converter output terminal, a DC output voltage having a desired voltage level from the DC input voltage supplied to the input terminal,
wherein the output terminal can charge an external battery or supply power to an external power-reception-side system by using the DC output voltage,
wherein the power supply switch transistor enables electric conduction between the output terminal and the converter output terminal of the DC-DC converter,
wherein the current limiting circuit limits a load current of the power supply switch transistor flowing from the converter output terminal to the output terminal,
wherein the input voltage detecting circuit generates an input voltage detection signal according to detection of the level of the DC input voltage supplied to the input terminal and supplies the input voltage detection signal to the current limiting circuit,
wherein the current limiting circuit controls the value of maximum current by the current limit of the power supply switch transistor in response to the input voltage detection signal supplied from the input voltage detection circuit,
wherein in the case where the DC input voltage supplied to the input terminal is at the high level, the current limiting circuit controls the value of the maximum current by the current limit of the power supply switch transistor to large current in response to the input voltage detection signal, and
wherein in the case where the DC input voltage supplied to the input terminal is at a level lower than the high level, the current limiting circuit controls the value of maximum current by the current limit of the power supply switch transistor to a current smaller than the large current in response to the input voltage detection signal.

2. The semiconductor integrated circuit according to claim 1 , wherein the power supply switch transistor is a P-channel MOS transistor whose source and drain are coupled to the converter output terminal and the output terminal, respectively.

3. The semiconductor integrated circuit according to claim 2 , wherein the gate of the P-channel MOS transistor of the power supply switch transistor is controlled by the current limiting circuit.

4. The semiconductor integrated circuit according to claim 3 ,
wherein the current limiting circuit includes a control P-channel MOS transistor, a detection resistor, and a differential amplifier,
wherein the source and drain of the control P-channel MOS transistor are coupled to the converter output terminal and one end of the detection resistor, respectively, the other end of the detection resistor is coupled to grounding potential,
wherein a reference voltage, the input voltage detection signal, and a detection voltage of the one end of the detection resistor are supplied to a first inversion input terminal, a second inversion input terminal, and a non-inversion input terminal of the differential amplifier, respectively,
wherein the gate of the P-channel MOS transistor and a gate of the control P-channel MOS transistor are controlled by an output signal of the differential amplifier, and
wherein the differential amplifier selects a low voltage level from the reference voltage of the first inversion input terminal and the input voltage detection signal of the second inversion input terminal, and the output signal of the differential amplifier controls drain current of the control P-channel MOS transistor so that the detection voltage of a non-inversion input terminal matches the selected low voltage level.

5. The semiconductor integrated circuit according to claim 4 ,
wherein in the case where level of the reference voltage of the first inversion input terminal is lower than that of the input voltage detection signal of the second inversion input terminal, drain current of the control P-channel MOS transistor is controlled so that the detection voltage matches the reference voltage, and
wherein in the case where the level of the input voltage detection signal of the second inversion input terminal is lower than that of the reference voltage of the first inversion input terminal, the drain current of the control P-channel MOS transistor is controlled so that the detection voltage matches the input voltage detection signal.

6. The semiconductor integrated circuit according to claim 5 ,
wherein the current limiting circuit further includes an offset voltage circuit for generating first and second offset voltages, and
wherein a first sum voltage of the first offset voltage and the detection voltage is supplied to the non-inversion input terminal of the differential amplifier, and a second sum voltage of the second offset voltage and the reference voltage is supplied to the first inversion input terminal of the differential amplifier.

7. The semiconductor integrated circuit according to claim 6 ,
wherein the current limiting circuit further includes a voltage control circuit having a voltage comparison amplifier and a comparison control transistor,
wherein first and second input terminals of the voltage comparison amplifier are coupled to the drain of the P-channel MOS transistor of the power supply switch transistor and the drain of the control P-channel MOS transistor, respectively, and
wherein an output terminal of the voltage comparison amplifier is coupled to a control input terminal of the comparison control transistor, and an output current path of the comparison control transistor is coupled between the drain of the control P-channel MOS transistor and the one end of the detection resistor.

8. The semiconductor integrated circuit according to claim 7 ,
wherein the input voltage detection circuit includes first and second voltage dividing resistors,
wherein the DC input voltage to be supplied to the input terminal is supplied to one end of the first voltage dividing resistor, the other end of the first voltage dividing resistor is coupled to one end of the second voltage dividing resistor, and the other end of the second voltage dividing resistor is coupled to grounding potential, and
wherein the input voltage detection signal is generated from a coupling node between the other end of the first voltage dividing resistor and the one end of the second voltage dividing resistor of the input voltage detection circuit.

9. The semiconductor integrated circuit according to claim 8 , further comprising a low-pass filter including a resistive element and a capacitive element,
wherein the input voltage detection signal generated from the input voltage detection circuit is supplied to an input terminal of the low-pass filter, and the input voltage detection signal transmitted to the output terminal of the low-pass filter is supplied to the second inversion input terminal of the current limiting circuit.

10. The semiconductor integrated circuit according to claim 9 , wherein an RF signal by NFC and an RF signal by wireless power supply can be supplied in a time division manner to the input terminal.

11. The semiconductor integrated circuit according to claim 10 , further comprising a linear regulator coupled in parallel to the DC-DC converter coupled between the input terminal and the output terminal,
wherein the linear regulator promptly operates in response to supply of the DC input voltage of the input terminal, and
wherein

Assignees

• Renesas Electronics Corp

Inventors

• Kayama Masanori

Classifications

• H02J7/96

  in response to battery voltage · CPC title

• H02J2207/40

  adapted for charging from various sources, e.g. AC, DC or multivoltage · CPC title

• H02J7/00

  Circuit arrangements for charging or discharging batteries or for supplying loads from batteries · CPC title

• H02M1/10 Primary

  Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from AC or DC · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title