Thin film transistor

US9343586B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9343586-B2
Application numberUS-201314399378-A
CountryUS
Kind codeB2
Filing dateJun 6, 2013
Priority dateJun 6, 2012
Publication dateMay 17, 2016
Grant dateMay 17, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%.

First claim

Opening claim text (preview).

The invention claimed is: 1. A thin film transistor, comprising; a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a passivation film configured to protect the source-drain electrode, on a substrate in this order, wherein the oxide semiconductor layer is a laminate comprising: a first oxide semiconductor layer consisting of In, Ga, Zn, Sn, and O; and a second oxide semiconductor layer consisting of In, Zn, Sn, and O, wherein the second oxide semiconductor layer is formed on the gate insulating film; the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film; and the contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are: In: smaller than or equal to 25 atomic %, excluding 0 atomic %; Ga: larger than or equal to 5 atomic %; Zn: larger than or equal to 35 atomic % and smaller than or equal to 65 atomic %; and Sn: larger than or equal to 8 atomic % and smaller than or equal to 30 atomic %. 2. The thin film transistor according to claim 1 , wherein the contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are: In: smaller than or equal to 20 atomic %, excluding 0 atomic %; Ga: larger than or equal to 15 atomic % and smaller than 50 atomic %; Zn: larger than or equal to 35 atomic % and smaller than or equal to 65 atomic %; and Sn: larger than or equal to 8 atomic % and smaller than or equal to 30 atomic %. 3. The thin film transistor according to claim 1 , wherein an etching rate of the first oxide semiconductor layer to a wet etchant for the source-drain electrode is smaller than or equal to one half of an etching rate of the source-drain electrode. 4. The thin film transistor according to claim 1 , wherein a thickness of the second oxide semiconductor layer is larger than or equal to 0.5 nm. 5. A display device, comprising the thin film transistor according to claim 1 . 6. The thin film transistor according to claim 2 , wherein an etching rate of the first oxide semiconductor layer to a wet etchant for the source-drain electrode is smaller than or equal to one half of an etching rate of the source-drain electrode. 7. The thin film transistor according to claim 2 , wherein a thickness of the second oxide semiconductor layer is larger than or equal to 0.5 nm. 8. A display device, comprising the thin film transistor according to claim 2 . 9. A thin film transistor, comprising; a gate electrode, a gate insulating film, an oxide semiconductor layer, an etch stopper layer, a source-drain electrode, and a passivation film configured to protect the source-drain electrode, on a substrate in this order, wherein the oxide semiconductor layer is a laminate comprising: a first oxide semiconductor layer consisting of In, Ga, Zn, Sn, and O; and a second oxide semiconductor layer consisting of In, Zn, Sn, and O, wherein the contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are: In: smaller than or equal to 25 atomic %, excluding 0 atomic %; Ga: larger than 30 atomic % and smaller than 50 atomic %; Zn: larger than or equal to 30.0 atomic % and smaller than or equal to 65 atomic %; and Sn: larger than or equal to 5 atomic % and smaller than or equal to 30 atomic %. 10. The thin film transistor according to claim 9 , wherein the contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are: In: smaller than or equal to 20 atomic %, excluding 0 atomic %; Ga: larger than 30 atomic % and smaller than 50 atomic %; Zn: larger than or equal to 35 atomic % and smaller than or equal to 65 atomic %; and Sn: larger than or equal to 8 atomic % and smaller than or equal to 30 atomic %. 11. The thin film transistor according to claim 9 , wherein the second oxide semiconductor layer is formed on the gate insulating film; and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the etch stopper layer. 12. The thin film transistor according to claim 9 , wherein a thickness of the second oxide semiconductor layer is larger than or equal to 0.5 nm. 13. A display device, comprising the thin film transistor according to claim 9 . 14. The thin film transistor according to claim 9 , wherein the content of Ga relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer is equal to or larger than 33 atomic % and smaller than 50 atomic %. 15. The thin film transistor according to claim 9 , wherein the content of Ga relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer is equal to or larger than 38 atomic % and smaller than 50 atomic %. 16. The thin film transistor according to claim 9 , wherein the content of Ga relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer is larger than 40 atomic % and smaller than 50 atomic %. 17. The thin film transistor according to claim 10 , wherein the second oxide semiconductor layer is formed on the gate insulating film; and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the etch stopper layer. 18. The thin film transistor according to claim 10 , wherein a thickness of the second oxide semiconductor layer is larger than or equal to 0.5 nm. 19. A display device, comprising the thin film transistor according to claim 10 .

Assignees

Inventors

Classifications

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

  • Oxides · CPC title

  • using physical deposition, e.g. vacuum deposition or sputtering · CPC title

  • characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

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What does patent US9343586B2 cover?
Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comp…
Who is the assignee on this patent?
Kobe Steel Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 17 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).