Semiconductor device

Patent metadata

Field	Value
Publication number	US-9343579-B2
Application number	US-201414279374-A
Country	US
Kind code	B2
Filing date	May 16, 2014
Priority date	May 20, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first insulating layer including a groove;
a gate electrode layer at least in a bottom of the groove;
a gate insulating layer over and in contact with the gate electrode layer to cover the groove and at least part of a top of the first insulating layer;
an oxide semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween;
a source electrode layer and a drain electrode layer over the first insulating layer with the gate insulating layer interposed therebetween, the source electrode layer and the drain electrode layer electrically connected to the oxide semiconductor layer; and
a second insulating layer over the gate insulating layer to cover the source electrode layer and the drain electrode layer,
wherein each of the gate insulating layer and the second insulating layer includes an aluminum oxide film containing excess oxygen.

2. The semiconductor device according to claim 1 , wherein the gate insulating layer covers a side and a bottom of the oxide semiconductor layer in the groove.

3. The semiconductor device according to claim 1 , wherein the gate insulating layer and the second insulating layer are in contact with each other in a region where the source electrode layer and the drain electrode layer do not exist.

4. The semiconductor device according to claim 1 , further comprising:
a first oxide layer between the gate insulating layer and the oxide semiconductor layer; and
a second oxide layer between the oxide semiconductor layer and the second insulating layer,
wherein each of the first oxide layer and the second oxide layer comprises one of metal elements contained in the oxide semiconductor layer.

5. The semiconductor device according to claim 4 , wherein the second oxide layer is over the source electrode layer and the drain electrode layer to cover the oxide semiconductor layer not covered with the source electrode layer and the drain electrode layer.

6. The semiconductor device according to claim 1 , wherein the aluminum oxide film containing excess oxygen is an AlO x film (x>1.5).

7. A semiconductor device comprising:
a gate electrode layer;
a first insulating layer covering at least end portions of the gate electrode layer, and the first insulating layer including a groove;
a gate insulating layer over and in contact with the gate electrode layer to cover the groove and at least part of a top of the first insulating layer;
an oxide semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween;
a source electrode layer and a drain electrode layer over the first insulating layer with the gate insulating layer interposed therebetween, the source electrode layer and the drain electrode layer electrically connected to the oxide semiconductor layer; and
a second insulating layer over the gate insulating layer to cover the source electrode layer and the drain electrode layer,
wherein each of the gate insulating layer and the second insulating layer includes an aluminum oxide film containing excess oxygen.

8. The semiconductor device according to claim 7 , wherein the gate insulating layer covers a side and a bottom of the oxide semiconductor layer in the groove.

9. The semiconductor device according to claim 7 , wherein the gate insulating layer and the second insulating layer are in contact with each other in a region where the source electrode layer and the drain electrode layer do not exist.

10. The semiconductor device according to claim 7 , further comprising:
a first oxide layer between the gate insulating layer and the oxide semiconductor layer; and
a second oxide layer between the oxide semiconductor layer and the second insulating layer,
wherein each of the first oxide layer and the second oxide layer comprises one of metal elements contained in the oxide semiconductor layer.

11. The semiconductor device according to claim 10 , wherein the second oxide layer is over the source electrode layer and the drain electrode layer to cover the oxide semiconductor layer not covered with the source electrode layer and the drain electrode layer.

12. The semiconductor device according to claim 7 , wherein the aluminum oxide film containing excess oxygen is an AlO x film (x>1.5).

13. A semiconductor device comprising:
a first insulating layer including a groove;
a first gate electrode layer at least in a bottom of the groove;
a first gate insulating layer over and in contact with the first gate electrode layer to cover the groove and at least part of a top of the first insulating layer;
an oxide semiconductor layer overlapping with the first gate electrode layer with the first gate insulating layer interposed therebetween;
a source electrode layer and a drain electrode layer over the first insulating layer with the first gate insulating layer interposed therebetween, the source electrode layer and the drain electrode layer electrically connected to the oxide semiconductor layer;
a second gate insulating layer in contact with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;
a second gate electrode layer overlapping with the oxide semiconductor layer with the second gate insulating layer interposed therebetween; and
a second insulating layer covering the source electrode layer, the drain electrode layer, and the second gate electrode layer,
wherein each of the first gate insulating layer and the second insulating layer includes an aluminum oxide film containing excess oxygen.

14. The semiconductor device according to claim 13 , wherein the first gate insulating layer covers a side and a bottom of the oxide semiconductor layer in the groove.

15. The semiconductor device according to claim 13 , wherein the first gate insulating layer and the second insulating layer are in contact with each other in a region where the source electrode layer and the drain electrode layer do not exist.

16. The semiconductor device according to claim 13 , further comprising:
a first oxide layer between the first gate insulating layer and the oxide semiconductor layer; and
a second oxide layer between the oxide semiconductor layer and the second gate insulating layer,
wherein each of the first oxide layer and the second oxide layer comprises one of metal elements contained in the oxide semiconductor layer.

17. The semiconductor device according to claim 16 , wherein the second oxide layer is over the source electrode layer and the drain electrode layer to cover the oxide semiconductor layer not covered with the source electrode layer and the drain electrode layer.

18. The semiconductor device according to claim 13 , wherein the aluminum oxide film containing excess oxygen is an AlO x film (x>1.5).

19. A semiconductor device comprising:
a first gate electrode layer;
a first insulating layer covering at least end portions of the first gate electrode layer, and the first insulating layer including a groove;
a first gate insulating layer over and in contact with the first gate electrode layer to cover the groove and at least part of a top of the first insulating layer;
an oxide semiconductor layer overlapping with the first gate electrode layer with the first gate insulating layer interposed therebetween;
a source electrode layer and a drain electrode layer over the first insulating layer with the first gate insulating layer interposed therebetween, the source electrode layer and the drain electrode layer

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Suzawa Hideomi
• Okazaki Yutaka

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title