Deep trench isolation

Patent metadata

Field	Value
Publication number	US-9343526-B2
Application number	US-201313801514-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.

First claim

What is claimed is:

1. A method, comprising:
forming a buried layer over a substrate of a first conductivity type;
forming a first isolation trench around an isolated region, the isolated region being disposed over a first portion of the buried layer;
forming a second isolation trench around the first isolation trench; and
forming a punch-through structure between at least a portion of the first isolation trench and a portion of the second isolation trench by:
forming a first region over a second portion of the buried layer, the first region having the first conductivity type, and
forming a second region located over the first region, the second region having a second conductivity type.

2. The method of claim 1 , wherein, when the isolated region is set to a greater than zero potential with respect to the substrate, a voltage across the second portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.

3. The method of claim 1 , wherein the isolated region has a conductivity type opposite of the substrate conductivity type.

4. The method of claim 3 , including forming a second punch-through structure around the second isolation trench, the second punch-through structure including a third portion of the buried layer.

5. The method of claim 4 , wherein, when the isolated region is set to the greater than zero potential with respect to the substrate, a voltage across the third portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.

6. The method of claim 4 , wherein forming the second punch-through structure:
forming a third region over the third portion of the buried layer, the third region having the first conductivity type, and
forming a fourth region over the third region, the fourth region having the second conductivity type.

7. The method of claim 6 , wherein a depth of the first region of the first punch-through structure is greater than a depth of the third region of the second punch-through structure.

Assignees

• Freescale Semiconductor Inc

Inventors

• Cheng Xu
• Blomberg Daniel J
• Zhang Zhihong
• Zuo Jiang-Kai

Classifications

• H10W10/0148

  comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/40

  Isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title