Ceramic powder, semiconductor ceramic capacitor, and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9343522-B2
Application number	US-201314100116-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Jun 22, 2011
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A ceramic powder for use in a grain boundary insulated semiconductor ceramic that has an excellent ESD withstanding voltage, a semiconductor ceramic capacitor using the ceramic powder, and a manufacturing method therefor. The ceramic powder for use in a SrTiO 3 based grain boundary insulated semiconductor ceramic has a specific surface area of 4.0 m 2 /g or more and 8.0 m 2 /g or less, and a cumulative 90% grain size D90 of 1.2 μm or less.

First claim

The invention claimed is:

1. A semiconductor ceramic capacitor comprising:
a laminated body comprising a plurality of semiconductor ceramic layers and a plurality of internal electrodes containing Ni as their main constituent, the internal electrodes located along interfaces between adjacent semiconductor ceramic layers of the plurality of semiconductor ceramic layers; and
external electrodes on opposed ends of the laminated body and electrically connected to respective sets of the plurality of internal electrodes,
wherein the semiconductor ceramic layers comprise, before sintering, a SrTiO 3 ceramic powder having a specific surface area of 4.0 m 2 /g or more and 8.0 m 2 /g or less, and a cumulative 90% grain size D90 of 1.2 μm or less.

2. The semiconductor ceramic capacitor according to claim 1 , wherein a ratio between Sr and Ti is 0.990 or more and 1.010 or less in the SrTiO 3 ceramic powder.

3. The semiconductor ceramic capacitor according to claim 1 , further comprising a donor element in the SrTiO 3 ceramic powder.

4. The semiconductor ceramic capacitor according to claim 3 , wherein a molar content of the donor element is 0.2 to 1.2 mol with respect to 100 mol of Ti.

5. The semiconductor ceramic capacitor according to claim 3 , wherein a molar content of the donor element is 0.4 to 1.0 mol with respect to 100 mol of Ti.

6. The semiconductor ceramic capacitor according to claim 3 , wherein the donor element is selected from the group consisting of La, Sm, Dy, Ho, Y, Nd, and Ce, and Nb, Ta, and W.

7. The semiconductor ceramic capacitor according to claim 3 , further comprising an acceptor element in the SrTiO 3 ceramic powder.

8. The semiconductor ceramic capacitor according to claim 7 , wherein a molar content of the acceptor element is 0.7 mol or less and greater than 0 mol with respect to 100 mol of Ti.

9. The semiconductor ceramic capacitor according to claim 7 , wherein a molar content of the acceptor element is 0.3 to 0.5 mol with respect to 100 mol of Ti.

10. The semiconductor ceramic capacitor according to claim 7 , wherein the acceptor element is selected from the group consisting of Mn, Co, Ni, and Cr.

11. The semiconductor ceramic capacitor according to claim 7 , wherein a molar content of the donor element is 0.2 to 1.2 mol with respect to 100 mol of Ti, and a molar content of the acceptor element is 0.7 mol or less and greater than 0 mol with respect to 100 mol of Ti.

Assignees

• Murata Manufacturing Co

Inventors

• Kawamoto Mitsutoshi
• Sano Atsushi
• Ishikawa Tatsuya
• Kobayashi Yasutomo
• Fujita Yoshihiro
• Kimura Yuki
• Kusano Yuichi

Classifications

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• C04B2235/5454

  nanometer sized, i.e. below 100 nm · CPC title

• H01L28/55 Primary

  Electricity · mapped topic

• C04B2235/5436

  micrometer sized, i.e. from 1 to 100 micron · CPC title

• C04B2235/5445

  submicron sized, i.e. from 0,1 to 1 micron · CPC title