Interconnect layer and method for manufacturing the same
US-2024420994-A1 · Dec 19, 2024 · US
US9343408B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9343408-B2 |
| Application number | US-201314075228-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 8, 2013 |
| Priority date | Nov 8, 2013 |
| Publication date | May 17, 2016 |
| Grant date | May 17, 2016 |
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Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H 2 SO 4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
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What is claimed is: 1. A method comprising providing a substrate; forming a dielectric layer above the substrate; forming a plurality of trenches in the dielectric layer; forming a liner layer above the dielectric layer in the trenches, wherein the liner layer comprises at least one of Ta or TaN; forming a copper layer above the liner layer, wherein the copper layer fills in the trenches; planarizing the liner layer and the copper layer so that a portion of the liner layer and copper layers are removed to expose the dielectric layer; applying an etch solution to the substrate, wherein the etch solution comprises HF, H 2 SO 4 , and H 2 O, wherein a concentration of HF is between 0.5 and 0.8 vol %, and wherein a concentration of H 2 SO 4 is between 21 and 28 vol %. 2. A method as in claim 1 wherein the etch solution selectively etches the copper layer with respect to the liner layer, wherein the copper layer is etched between 2 and 3 nm, wherein the liner layer is etched between 1.5 and 2 nm. 3. A method as in claim 1 wherein the etch solution comprises HF:H 2 SO 4 :H 2 O at 1:1:2 volume ratio using 2.5 vol % HF and 96-98 vol % H 2 SO 4 . 4. A method as in claim 1 wherein the etch solution is applied for a time between 30 and 60 seconds. 5. A method as in claim 1 wherein the etch solution is at a temperature between 25 and 40 C. 6. A method as in claim 1 further comprising rinsing the substrate in water. 7. A method as in claim 1 wherein rinsing the substrate in water is at a temperature between 15 and 35 C for a time between 60 and 120 seconds. 8. A method as in claim 1 wherein the planarizing process is performed by a chemical mechanical polishing process. 9. A method as in claim 1 further comprising forming a SiC layer on the dielectric layer. 10. A method as in claim 9 wherein the thickness of the SiC layer is between 10 nm and 100 nm. 11. A method comprising providing a substrate; forming a dielectric layer above the substrate; forming a plurality of trenches in the dielectric layer; forming a liner layer above the dielectric layer in the trenches, wherein the liner layer comprises at least one of Ta or TaN; forming a copper layer above the liner layer, wherein the copper layer fills in the trenches; planarizing the liner layer and the copper layer so that a portion of the liner layer and copper layers are removed to expose the dielectric layer; applying an etch solution to the substrate, wherein the etch solution comprises HF, H 2 SO 4 , and H 2 O, wherein a concentration of HF is between 0.3 and 0.5 vol %, and wherein a concentration of H 2 SO 4 is between 14 and 18 vol %. 12. A method as in claim 11 wherein the etch solution comprises HF:H 2 SO 4 :H 2 O at 1:1:4 volume ratio using 2.5 vol % HF and 96-98 vol % H 2 SO 4 . 13. A method as in claim 11 wherein the etch solution is applied for a time between 30 and 60 seconds, wherein the etch solution is at a temperature between 25 and 40 C. 14. A method as in claim 11 further comprising rinsing the substrate in water for a time between 60 and 120 seconds, wherein the water is at a temperature between 15 and 35 C. 15. A method as in claim 11 further comprising forming a SiC layer on the dielectric layer.
by liquid etching only · CPC title
Barrier, adhesion or liner layers · CPC title
on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title
by filling conductive material into holes, grooves or trenches · CPC title
comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title
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