Semiconductor device and manufacturing method of same

Patent metadata

Field	Value
Publication number	US-9343395-B2
Application number	US-201313924938-A
Country	US
Kind code	B2
Filing date	Jun 24, 2013
Priority date	Jul 17, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an electrode pad formed over a first portion of a substrate;
a polyimide layer formed over a second portion of the substrate, the polyimide layer does not overlap the electrode pad in a cross-sectional view;
a Cu film formed over the electrode pad and a portion of the polyimide layer;
a Ni film formed adjacent to the upper surface of the Cu film; and
a Pd film formed adjacent to the upper surface of the Ni film and having a film thickness less than that of the Ni film and greater than or equal to 0.2 μm and less than 1 μm,
wherein a bonding wire consisting essentially of Au is directly coupled to an upper surface of the Pd film that is over the second portion of the substrate,
wherein the thickness of the Cu film is greater than each of the Ni film and the Pd film, and
wherein the semiconductor device is sealed with a resin.

2. A manufacturing method a semiconductor device, comprising:
(a) providing a semiconductor substrate having an electrode pad exposed from the upper surface of the semiconductor substrate;
(b) forming a polyimide layer over the substrate and using patterning to expose the electrode pad, the polyimide layer is not formed over a portion of the electrode pad;
(c) forming a seed film in contact with the polyimide layer and the upper surface of the electrode pad exposed from the upper surface of the semiconductor substrate;
(d) forming a resist pattern over the seed film;
(e) forming a Cu film, an Ni film, and a Pd film successively over the seed film exposed from the resist pattern by using plating, the Pd film having a film thickness less than that of the Ni film and greater than or equal to 0.2 μm and less than 1 μm, and the thickness of the Cu film is greater than each of the Ni film and the Pd film;
(f) after the step (e), removing the resist pattern;
(g) directly coupling a bonding wire consisting essentially of Au to an upper surface of the Pd film that is over the second portion of the substrate; and
(h) sealing the semiconductor device with a resin.

Assignees

• Renesas Electronics Corp

Inventors

• Shigihara Hisao
• Shigihara Hiromi
• Yajima Akira
• Tsukamoto Hiroshi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title