Power semiconductor device

Patent metadata

Field	Value
Publication number	US-9343388-B2
Application number	US-201214364189-A
Country	US
Kind code	B2
Filing date	Jan 25, 2012
Priority date	Jan 25, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate; semiconductor elements for electric power which are affixed to the surface of the front-surface electrode pattern; a partition wall which is provided on the front-surface electrode pattern so as to enclose the semiconductor elements for electric power; a first sealing resin member which is filled inside the partition wall; a second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein an electrode for a relay terminal is provided on a surface of the partition wall, and a wiring from inside of the partition wall to outside of the partition wall is led out via the electrode for a relay terminal.

First claim

The invention claimed is:

1. A power semiconductor device comprising:
a semiconductor-element substrate including an insulation substrate, a front-surface electrode pattern formed on a surface of the insulating substrate, and a back-surface electrode pattern formed on another surface of the insulating substrate;
a semiconductor element for electric power which is affixed, by using a bonding material, to the surface of the front-surface electrode pattern opposite the insulating substrate;
a partition wall which is provided on the front-surface electrode pattern by bonding, and encloses the semiconductor element for electric power;
a first sealing resin member which is filled inside the partition wall, and covers the semiconductor element for electric power and the front-surface electrode pattern in the partition wall; and
a second sealing resin member which covers the partition wall, the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall,
wherein a modulus of elasticity of the second sealing resin member is smaller than a modulus of elasticity of the first sealing resin member, and
wherein an electrode for a relay terminal which is separate from the front-surface electrode pattern is disposed on a surface of the partition wall,
the power semiconductor device further comprising a first wiring from inside of the partition wall to the electrode for a relay terminal, and second wiring, which is thicker than the first wiring, from the electrode for the relay terminal to outside of the partition wall,
wherein the first wiring is entirely covered with the first sealing resin member and the second wiring is covered with the second sealing resin member.

2. A power semiconductor device according to claim 1 , wherein a modulus of elasticity of the first sealing resin member is in a range of 1 GPa to 20 GPa, and a coefficient of linear thermal expansion of the first sealing resin member is in a range of 10 ppm to 30 ppm.

3. A power semiconductor device according to claim 1 , wherein the difference of between the coefficient of linear thermal expansion of the partition wall and the coefficient of linear thermal expansion of the first sealing resin member is 50 ppm or lower.

4. A power semiconductor device according to claim 1 ,
wherein a modulus of elasticity of the second sealing resin member is in a range of 30 kPa to 3 GPa.

5. A power semiconductor device according to claim 1 ,
wherein at least one of wires which connect the semiconductor element for electric power and the electrode for a relay terminal is thinner than other wires.

6. A power semiconductor device according to claim 5 , wherein a cross section of the wire which is thinner than other wires is 0.018 mm 2 or lower, and 50% or more of the thin wire is covered with the first sealing resin member.

7. A power semiconductor device according to claim 1 , wherein the semiconductor element for electric power is formed of a wide band gap semiconductor.

8. A power semiconductor device according to claim 7 , wherein the wide band gap semiconductor is a semiconductor selecting from silicon carbide, gallium nitride based material and diamond.

9. A power semiconductor device according to claim 1 , further comprising:
a case accommodating the semiconductor-element substrate, the semiconductor element, and the partition wall,
wherein the second sealing resin member is filled inside the case.

10. A power semiconductor device according to claim 1 ,
wherein the second sealing member resin member covers an outside of and top of the partition wall.

Assignees

• Terai Mamoru
• Ota Tatsuo
• Ikuta Hiroya
• Hayashi Kenichi
• Nishimura Takashi
• Shinohara Toshiaki
• Mitsubishi Electric Corp

Inventors

• Terai Mamoru
• Ota Tatsuo
• Ikuta Hiroya
• Hayashi Kenichi
• Nishimura Takashi
• Shinohara Toshiaki

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title