Package on package structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9343387-B2
Application number	US-201414452871-A
Country	US
Kind code	B2
Filing date	Aug 6, 2014
Priority date	Mar 5, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.

First claim

What is claimed is:

1. A package on package (PoP) structure, comprising:
a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and
an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a plurality of conductive posts formed on and in contact with the electrode pads, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, each of the conductive posts and the corresponding conductive bump forming a conductive element.

2. The structure of claim 1 , wherein each of the conductive bumps further has an insulating body formed inside the metal ball.

3. The structure of claim 1 , wherein the electronic element is another packaging substrate or a semiconductor element.

4. The structure of claim 1 , further comprising a semiconductor element disposed on the packaging substrate.

5. The structure of claim 4 , wherein the semiconductor element is positioned between the electronic element and the packaging substrate.

6. The structure of claim 4 , further comprising an underfill formed between the packaging substrate and the semiconductor element.

7. The structure of claim 1 , further comprising an encapsulant formed between the electronic element and the packaging substrate for encapsulating the conductive elements.

8. The structure of claim 1 , further comprising an encapsulant formed on the packaging substrate for encapsulating the conductive bumps and having a plurality of openings for exposing the conductive bumps to be bonded with the conductive posts.

9. A method for fabricating a package on package (PoP) structure, comprising the steps of:
providing a packaging substrate having a plurality of conductive bumps and an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a plurality of conductive posts formed on and in contact with the electrode pads, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and
correspondingly bonding the conductive posts to the conductive bumps so as to stack the electronic element on the packaging substrate, wherein each of the conductive posts and the corresponding conductive bump form a conductive element.

10. The method of claim 9 , wherein each of the conductive bumps further has an insulating body formed inside the metal ball.

11. The method of claim 9 , wherein the electronic element is another packaging substrate or a semiconductor element.

12. The method of claim 9 , further comprising disposing a semiconductor element on the packaging substrate.

13. The method of claim 12 , wherein the semiconductor element is positioned between the electronic element and the packaging substrate.

14. The method of claim 12 , further comprising forming an underfill between the packaging substrate and the semiconductor element.

15. The method of claim 9 , after correspondingly bonding the conductive posts to the conductive bumps, further comprising forming an encapsulant between the electronic element and the packaging substrate for encapsulating the conductive elements.

16. The method of claim 9 , before correspondingly bonding the conductive posts to the conductive bumps, further comprising forming an encapsulant on the packaging substrate for encapsulating the conductive bumps and forming a plurality of openings in the encapsulant for exposing the conductive bumps.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Hsu Chu-Chi
• Wang Lung-Yuan
• Chiang Cheng-Chia
• Shih Chia-Kai
• Huang Shu-Huei

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title