High voltage semiconductor devices including electric arc suppression material and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9343383-B2
Application number	US-201213410788-A
Country	US
Kind code	B2
Filing date	Mar 2, 2012
Priority date	Mar 2, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess.

First claim

What is claimed:

1. A high voltage semiconductor device comprising:
a high voltage semiconductor device package including a wall defining a recess within the high voltage semiconductor device package;
a high voltage semiconductor chip in the recess; and
a high voltage electric arc suppression material comprising SOF 2 , SO 2 F 2 , SF 6 , and/or S 2 F 10 in the recess, wherein high voltage comprises at least about 600 Volts.

2. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device comprises a Silicon Carbide (SiC) MOSFET.

3. The high voltage semiconductor device of claim 2 wherein the SiC MOSFET comprises a 20 amp SiC MOSFET wherein the high voltage semiconductor chip measures about 4 mm on a side thereof.

4. The high voltage semiconductor device of claim 2 wherein the SiC MOSFET comprises a 40 amp SiC MOSFET wherein the high voltage semiconductor chip measures about 8 mm on a side thereof.

5. The high voltage semiconductor device of claim 2 wherein the SiC MOSFET comprises a 100 amp SiC MOSFET wherein the high voltage semiconductor chip measures about 20 mm on a side thereof.

6. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device package comprises metal, metal coated plastic, high temperature plastic, and/or ceramic.

7. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device comprises a Si-Lateral-diffused MOS (LDMOS) transistor, a Bipolar junction transistor, a GaAs MESFET, a GaAs or GaAs/InGaP heterojunction bipolar transistor (HBTs), a SiC MESFET or a GaN HEMT.

8. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device comprises a SiC Schottky Diode.

9. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 600 Volts provided via a lead penetrating the wall.

10. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 1200 Volts provided via a lead penetrating the wall.

11. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 1700 Volts provided via a lead penetrating the wall.

12. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 3400 Volts provided via a lead penetrating the wall.

13. The high voltage semiconductor device of claim 1 wherein a volume defined by the recess comprises about 750 mL or less.

14. The high voltage semiconductor device of claim 1 wherein a length of the recess comprises about 15 mm or less and a width of the recess comprises about 10 mm or less.

15. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip comprises a two terminal device.

16. The high voltage semiconductor device of claim 15 wherein a path through the high voltage electric arc suppression material from a first terminal configured to couple to a high voltage to a second terminal configured to couple to a reference voltage for the device is about 5 mm or less.

17. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip comprises a three terminal device.

18. The high voltage semiconductor device of claim 17 wherein a path through the high voltage electric arc suppression material from a first terminal configured to couple to a high voltage to a second terminal configured to couple to a reference voltage for the device is about 5 mm or less.

19. The high voltage semiconductor device of claim 1 further comprising:
a wire lead penetrating the wall and configured for electrically coupling a voltage of at least about 600 Volts to the chip; and
a submount having the chip mounted thereon, wherein the high voltage electric arc suppression material comprises a liquid or gas material having a dielectric breakdown voltage sufficient to prevent an electric arc from the wire lead to the submount.

20. The high voltage semiconductor device of claim 1 wherein the high voltage electric arc suppression material is hermetically sealed in the recess.

21. A high voltage Silicon Carbide (SiC) semiconductor device comprising:
a metal semiconductor device package including a wall defining a recess within the metal semiconductor device package;
a high voltage SiC semiconductor chip, including a bonding surface thereon, the chip coupled to a submount surface in the recess, wherein high voltage comprises at least about 600 Volts;
a wire lead electrically coupled to the bonding surface on the chip; and
SF 6 in the recess located between the wire lead at the bonding surface and the submount surface.

22. The high voltage SiC semiconductor device of claim 21 wherein a distance between the wire lead at the bonding surface and the submount surface comprises about 5 mm or less.

23. The high voltage SiC semiconductor device of claim 21 wherein the chip comprises a SiC MOSFET measuring about 4 mm on a side thereof.

24. The high voltage SiC semiconductor device of claim 21 wherein the chip is configured for coupling to a voltage of at least about 600 Volts provided via the wire lead penetrating the wall.

25. The high voltage SiC semiconductor device of claim 21 wherein the chip is configured for coupling to a voltage of at least about 1200 Volts provided via the wire lead penetrating the wall.

26. The high voltage SiC semiconductor device of claim 21 wherein a volume defined by the recess comprises about 750 mm 3 or less.

27. The high voltage SiC semiconductor device of claim 21 wherein the chip is configured for coupling to a voltage of at least about 1700 Volts provided via the wire lead penetrating the wall.

28. The high voltage SiC semiconductor device of claim 21 wherein the chip is configured for coupling to a voltage of at least about 3400 Volts provided via the wire lead penetrating the wall.

29. A high voltage semiconductor device comprising:
a high voltage semiconductor device package including a wall defining a recess within the high voltage semiconductor device package;
a high voltage semiconductor chip in the recess; and
a high voltage electric arc suppression material in the recess comprising a liquid or gas material having a dielectric breakdown voltage sufficient to prevent an electric arc from the wire lead to a submount, wherein high voltage comprises at least about 600 Volts and wherein the high voltage electric arc suppression material comprises SOF 2 , SO 2 F 2 , SF 6 , and/or S 2 F 10 .

30. A method of packaging a high voltage semiconductor device comprising:
providing a high voltage semiconductor device package, including a wall defining a recess within the high voltage semiconductor device package, to an atmosphere including a high voltage electric arc suppression material;
mounting a high voltage semiconductor chip in the recess while exposed to the atmosphere; and
sealing the high voltage semiconductor device package to enclose the high voltage electric arc suppression material with the high voltage semiconductor chip in the recess, wherein high voltage comprises at least about 600 Volt

Assignees

• Mieczkowski Van
• Cree Inc

Inventors

• Mieczkowski Van

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title