Fabricating fin structures with doped middle portions

Patent metadata

Field	Value
Publication number	US-9343371-B1
Application number	US-201514725552-A
Country	US
Kind code	B1
Filing date	May 29, 2015
Priority date	Jan 9, 2015
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

First claim

What is claimed is:

1. A method comprising:
fabricating at least one fin structure, the at least one fin structure comprising a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising:
providing an isolation layer in contact with the lower portion of the at least one fin structure;
forming a doping layer above the isolation layer and in contact with the at least one fin structure; and
annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

2. The method of claim 1 , wherein the method comprises:
fabricating a transistor having a channel region, the channel region comprising the upper portion of the at least one fin structure, wherein the doped middle portion of the at least one fin structure reduces leakage current between the source region and the drain region of the transistor.

3. The method of claim 1 , wherein the at least one fin structure comprises at least one first fin structure and at least one second fin structure, and the fabricating comprises:
forming the doping layer with a first thickness in contact with the at least one first fin structure and a second thickness in contact with the at least one second fin structure; and
annealing the doping layer to form a first doped middle portion of the at least one first fin structure with the first thickness and a second doped middle portion of the at least one second fin structure with the second thickness, wherein the first thickness and the second thickness are different thicknesses.

4. The method of claim 3 , wherein the method comprises:
fabricating an integrated circuit comprising a first transistor and a second transistor, the first transistor comprising the at least one first fin structure and the second transistor comprising the at least one second fin structure, and the first thickness of the first doped middle portion the first transistor having a first threshold voltage characteristic and the second thickness of the second doped middle portion facilitates the second transistor having a second threshold voltage characteristic, wherein the first threshold voltage characteristic and the second threshold voltage characteristic are different threshold voltage characteristics.

5. The method of claim 1 , wherein the at least one fin structure comprises at least one first fin structure and at least one second fin structure, and the fabricating comprises:
forming the doping layer with first dopants in contact with the at least one first fin structure and second dopants in contact with the at least one second fin structure, wherein the first dopants and second dopants are different dopants; and
annealing the doping layer to form a first doped middle portion of the at least one first fin structure having the first dopants and a second doped middle portion of the at least one second fin structure having the second dopants.

6. The method of claim 5 , wherein the first dopants comprise n-type dopants and the second dopants comprise p-type dopants, and the method comprises:
fabricating an integrated circuit comprising a p-type transistor and an n-type transistor, the p-type transistor comprising the at least one first fin structure and the n-type transistor comprising the at least one second fin structure.

7. The method of claim 1 , wherein the at least one fin structure comprises at least one first fin structure and at least one second fin structure, and the fabricating comprises:
forming the doping layer with a first initial dopant concentration in contact with the at least one first fin structure and a second initial dopant concentration in contact with the at least one second fin structure, wherein the first initial dopant concentration and the second initial dopant concentration are different concentrations; and
annealing the doping layer to form a first middle portion of the at least one first fin structure with a first final dopant concentration and a second middle portion of the at least one second fin structure with a second final dopant concentration, wherein the first final dopant concentration and the second final dopant concentration are different dopant concentrations.

8. The method of claim 7 , wherein the method comprises:
fabricating an integrated circuit comprising a first transistor and a second transistor, the first transistor comprising the at least one first fin structure and the second transistor comprising the at least one second fin structure, and the first concentration of the dopants facilitates the first transistor having a first threshold voltage characteristic and the second concentration of the dopants facilitates the second transistor having a second threshold voltage characteristic, wherein the first threshold voltage characteristic and the second threshold voltage characteristic are different threshold voltage characteristics.

9. The method of claim 1 , wherein the fabricating comprises:
providing a substrate underlying the at least one fin structure;
implanting other dopants into the substrate to form a substrate well region thereof, wherein the other dopants and the dopants of the doping layer are different dopants.

10. The method of claim 1 , wherein the fabricating comprises fabricating the doped middle portion of the at least one fin structure without doping the upper portion or the lower portion of the at least one fin structure notwithstanding the diffusing of the dopants during the annealing.

11. The method of claim 1 , further comprising:
forming a conformal gate structure over the isolation material and in contact with the at least one fin structure, wherein the isolation material facilitates aligning the conformal gate structure in contact with the upper portion of the at least one fin structure but not in contact with the doped middle portion thereof.

12. The method of claim 1 , wherein providing the isolation layer comprises providing the isolation layer with a thickness, the thickness of the isolation layer setting the lower portion of the at least one fin structure with the thickness.

13. The method of claim 1 , wherein forming a doping layer comprises forming the doping layer with a thickness, the thickness of the doping layer setting the doped middle portion of the at least one fin structure with the thickness.

14. The method of claim 1 , wherein the annealing comprises oxidizing the doping layer and the at least one fin structure.

15. The method of claim 1 , wherein forming the doping layer comprises epitaxially forming a material over the at least one fin structure to form the doping layer.

16. The method of claim 15 , wherein the material comprises at least one of silicon or germanium.

17. The method of claim 1 , wherein forming the doping layer comprises providing a material, and concurrently therewith doping the material with the dopants, to form the doping layer.

18. The method of claim 17 , wherein the dopants comprise at least one of boron, phosphorous or arsenic.

19. The method of claim 1 , wherein forming the doping layer comprises providing a borophosphosilicate glass to form the doping layer.

20. The method of claim 1 , wherein a concentration of the dopants in the middle portion of the at least one fin structure is between 10 18 to 10 20 atoms per cm 3 .

Assignees

• Globalfoundries Inc

Inventors

• Wu Xusheng
• Liu Jin Ping

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title