Split gate nanocrystal memory integration

Patent metadata

Field	Value
Publication number	US-9343314-B2
Application number	US-201414291359-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

First claim

What is claimed is:

1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) cell in an NVM region, the method comprising:
forming a charge storage layer on the substrate;
depositing a first conductive layer over the charge storage layer;
depositing a capping layer over the first conductive layer;
patterning the capping layer, the first conductive layer, and the charge storage layer to form a control gate stack;
depositing a second conductive layer over the substrate including over the control gate stack;
patterning the second conductive layer to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack;
planarizing the first portion of the second conductive layer and the control gate stack to leave a dummy select gate from the first portion of the second conductive layer, wherein
the planarizing exposes a top surface of the dummy select gate, and
a top surface of a remaining portion of the first conductive layer of the control gate stack is lower relative to the top surface of the dummy select gate; and

replacing the dummy select gate with a select gate comprising metal, wherein the method further comprising replacing a portion of a first dielectric layer with a high-k dielectric prior to replacing the dummy select gate.

2. The method of claim 1 , further comprising:
forming an insulating sidewall spacer on sides of the control gate stack prior to the depositing the second conductive layer.

3. The method of claim 2 , further comprising:
forming the first dielectric layer on the substrate after the patterning the capping layer, the first conductive layer, and the charge storage layer and prior to the depositing the second conductive layer.

4. The method of claim 3 , wherein the first dielectric layer comprises one of a group consisting of thermal oxide and a high-k dielectric.

5. The method of claim 3 , wherein the patterning the second conductive layer further comprises etching the first dielectric layer to leave the portion of the first dielectric layer under the first portion of the second conductive layer.

6. The method of claim 1 , wherein the semiconductor structure further comprises a logic transistor in a logic region, further comprising:
removing the capping layer, the first conductive layer, and the charge storage layer from the logic region prior to depositing the second conductive layer.

7. The method of claim 6 , wherein the patterning the second conductive layer is further characterized by leaving a dummy logic gate in the logic region.

8. The method of claim 7 , further comprising replacing the dummy logic gate with a logic gate comprising metal.

9. The method of claim 8 , further comprising forming a first dielectric layer on the substrate in the NVM region and the logic region after the patterning the capping layer, the first conductive layer, and the charge storage layer and prior to the depositing the second conductive layer, wherein the first dielectric layer comprises one of a group consisting of oxide and a high-k dielectric.

10. The method of claim 8 further comprising forming a first dielectric layer on the substrate in the NVM region and the logic region after the patterning the capping layer, the first conductive layer, and the charge storage layer and prior to the depositing the second conductive layer, wherein the patterning the second conductive layer further comprises etching the first dielectric layer to leave a portion of the first dielectric layer under the dummy logic gate.

11. The method of claim 10 , further comprising replacing the first dielectric layer with a high-k dielectric prior to replacing the dummy logic gate.

12. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) structure in an NVM region, the method comprising:
forming a charge storage layer on the substrate;
depositing a first polysilicon layer over the charge storage layer;
depositing a capping layer over the first polysilicon layer;
patterning the capping layer, the first conductive layer, and the charge storage layer to leave a control gate stack comprising remaining portions of the capping layer, the first conductive layer, and the charge storage layer;
depositing a second polysilicon layer over the substrate including over the control gate stack;
patterning the second polysilicon layer to leave a first portion of the second polysilicon layer over a portion of the control gate stack and adjacent to a first side of the control gate stack;
planarizing the first portion of the second polysilicon layer and the control gate stack to leave a dummy select gate from the first portion of the second polysilicon layer, wherein a top surface of the control gate stack comprises a top surface of the remaining portion of the capping layer and wherein a top surface of the remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate; and
replacing the dummy select gate with a select gate comprising metal by using an etchant to remove the dummy select gate, wherein the etchant is highly selective to polysilicon and does not substantially remove the capping layer.

13. The method of claim 12 , wherein the semiconductor structure further comprises a logic transistor in a logic region, further comprising:
removing the capping layer, the first conductive layer, and the charge storage layer from the logic region prior to depositing the second conductive layer;
wherein:
the depositing the second polysilicon layer deposits the second polysilicon layer over the logic region;
the patterning the second polysilicon layer leaves a dummy logic gate comprising polysilicon over the substrate in the logic region;
the planarizing the first portion of second polysilicon layer leaves the dummy logic gate with a top surface coplanar with a top surface of the dummy select gate; and
the replacing the dummy select gate occurs simultaneously with replacing the dummy logic gate with a gate comprising metal.

Assignees

• Loiko Konstantin V
• Winstead Brian A
• Freescale Semiconductor Inc

Inventors

• Loiko Konstantin V
• Winstead Brian A

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title