Architecture and method for memory programming

Patent metadata

Field	Value
Publication number	US-9343169-B2
Application number	US-201414162278-A
Country	US
Kind code	B2
Filing date	Jan 23, 2014
Priority date	Oct 9, 2008
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

First claim

What is claimed is:

1. A method of reducing coupling effects in a programming operation in a memory, comprising:
communicating a status of a target data line stored in a page buffer associated with the target data line to each of two adjacent page buffers each associated with adjacent data lines to the target data line;
storing in each page buffer whether zero, one, or two data lines adjacent to its respective target data line are inhibited; and
applying a bias voltage to the target data line when at least one of the data lines adjacent to the target data line is inhibited.

2. The method of claim 1 , wherein applying a bias voltage further comprises:
applying a first bias voltage to the target data line when one of the data lines adjacent the target data line is inhibited; and
applying a second bias voltage higher than the first bias voltage to the target data line when both of the data lines adjacent the target data line are inhibited.

3. The method of claim 2 , wherein the first bias voltage is approximately 0.8 volts, and the second bias voltage is approximately 1.3 volts.

4. The method of claim 2 , wherein communicating a status of a target data line comprises:
connecting the page buffer associated with the target data line to each of its two adjacent page buffers using the target data line;
providing a first logic signal when the target data line is inhibited; and
providing a second logic signal when the target data line is not inhibited.

5. The method of claim 1 , wherein storing comprises latching a logic 1 value in a first latch of the page buffer when one adjacent data line is inhibited, and latching a logic 1 value in a second latch of the page buffer when both adjacent data lines are inhibited.

6. The method of claim 1 , wherein applying the first bias voltage further comprises biasing the target data line in response to the first latch being set at a logic 1 value, and wherein applying the second bias voltage further comprises biasing the target data line in response to the second latch being set at a logic 1 value.

7. The method of claim 6 , and further comprising:
latching in a program/inhibit latch a signal indicating whether the target data line is to be programmed or inhibited; and
inverting the program/inhibit latch when its latch signal indicates that the target data line is to be programmed and at least one of the first and the second latches is set at a logic 1 value.

8. A method of programming a memory, comprising:
latching a program or inhibit signal for each of a plurality of data lines in a program/inhibit latch of a respective one of a plurality of page buffers;
communicating the program/inhibit latch data in each page buffer to each of a subset of the plurality of page buffers for data lines adjacent to its respective page buffer; and
adjusting a data line voltage of each data line to be programmed when at least one of that data line's adjacent data lines is inhibited.

9. The method of claim 8 , wherein communicating comprises:
physically connecting each page buffer to a first of its two adjacent page buffers;
transmitting the latched program or inhibit signal of each page buffer to the first of its two adjacent page buffers;
storing the transmitted program or inhibit signal of each page buffer in the first of its two adjacent page buffers;
physically connecting each page buffer to the second of its two adjacent page buffers;
transmitting the latched program or inhibit signal of each page buffer to the second of its two adjacent page buffers; and
storing the transmitted program or inhibit signal of each page buffer in the second of its two adjacent page buffers.

10. The method of claim 9 , wherein adjusting a data line voltage comprises:
applying a first adjustment voltage to the data line of each page buffer that has one of its two adjacent data lines inhibited; and
applying a second adjustment voltage to the data line of each page buffer than has both of its two adjacent data lines inhibited.

11. A page buffer circuit, comprising:
a program/inhibit latch to store data indicative of whether a data line of the page buffer is to be programmed or inhibited;
first and second latches connected between the program/inhibit latch and the data line, the first latch to provide the data line a first voltage under a first condition, and the second latch to provide the data line a second voltage under a second condition.

12. The circuit of claim 11 , wherein the first and second latches are dynamic latches.

13. The circuit of claim 11 , wherein the first latch is operable to actuate application of the first voltage when the first latch is set, and wherein the second latch is operable to actuate application of the second voltage when the second latch is set.

14. The circuit of claim 11 , wherein the first and second latches accept external signals to set the latches.

15. A memory array architecture, comprising:
a first page buffer for a first data line;
a second page buffer for a second data line adjacent to the first data line;
a third page buffer for a third data line adjacent to the first data line;
first, second, and third clamp transistors respectively connected to the first, second, and third page buffers;
first and second multiplexer transistors connected in series between the first and second clamp transistors, control gates of the first and second multiplexer transistors respectively connected to first and second multiplexer circuits; and
third and fourth multiplexer transistors connected in series between the first and third clamp transistors, control gates of the third and fourth multiplexer transistors respectively connected to third and fourth multiplexer circuits.

16. A memory array architecture, comprising:
a plurality of page buffers, a page buffer for each data line of the memory array;
a plurality of multiplexer circuits, a multiplexer circuit for each of the plurality of page buffers;
a plurality of data line clamp transistors, each connected between one of the plurality of page buffers and its data line; and
a plurality of multiplexer transistors, each gate connected to one of the plurality of multiplexer circuits and between its respective data line clamp transistor and a multiplexer transistor of one of its two adjacent page buffers;
wherein each of the plurality of page buffers comprises:
a program/inhibit latch to store data indicative of whether a data line of the page buffer is to be programmed or inhibited;
first and second latches connected between the program/inhibit latch and the data line, the first latch to provide the data line a first voltage under a first condition, and the second latch to provide the data line a second voltage under a second condition.

17. The architecture of claim 16 , wherein the first and second latches are dynamic latches.

18. The architecture of claim 16 , wherein the first latch is operable to actuate application of the first voltage when the first latch is set, and wherein the second latch is operable to actuate application of the second voltage when the second latch is set.

19. The architecture of claim 16 , wherein the first and second latches accept external signals to set the latches.

20. A memory, comprising:
an array of memory cells;
circuitry for control and/or access of the array of memory cells; and
a page buffer for each of a plurality of data lines of the memory, each page buffer comprising:
a program/inhibit latch to store data indicative of whether the data line of the page bu

Assignees

• Micron Technology Inc

Inventors

• Vali Tommaso
• Santin Giovanni
• Incarnati Michele
• Moschiano Violante

Classifications

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• G11C2211/5646

  Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page" · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C2211/5642

  Multilevel memory with buffers, latches, registers at input or output · CPC title