Storage device, including nonvolatile memory and memory controller, operating method of storage device and method of accessing storage device

Patent metadata

Field	Value
Publication number	US-9343121-B2
Application number	US-201514608435-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	May 13, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

An operating method of a storage device is provided. The storage device includes a nonvolatile memory and a memory controller to control the nonvolatile memory. Temperature is detected. A current weighted time is calculated using the temperature. Data is read from the nonvolatile memory using a read voltage level which is adjusted based on the current weighted time. The current weighted time is determined according to an amount of charges leaked from memory cells storing the data at the temperature.

First claim

What is claimed is:

1. An operating method of a storage device which includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the operating method comprising:
detecting temperature;
calculating a current weighted time using the temperature; and
reading data from the nonvolatile memory using a read voltage level which is adjusted based on the current weighted time,
wherein the temperature is periodically detected at a first period, and the calculating of the current weighted time is periodically performed at a second period based on the detected temperature.

2. The operating method of claim 1 ,
wherein the calculating of the current weighted time comprises:
calculating a weighted elapse time by adjusting a time of the second period based on the detected temperature; and
calculating the current weighted time by adding the weighted elapse time to a previous weighted time.

3. The operating method of claim 2 , wherein the weighted elapse time increases in proportion to an increase in the detected temperature.

4. The operating method of claim 2 , wherein the weighted elapse time increases in proportion to an increase in the time of the second period by which the current weighted time is periodically calculated.

5. The operating method of claim 2 , wherein the time of the second period is further adjusted using a number of program-erase cycles performed on the storage device, and wherein the weighted elapse time increases in proportion to an increase in the number of program-erase cycles.

6. The operating method of claim 5 , wherein the number of program-erase cycles is an average number of performing erase operations on each of a plurality of memory blocks of the nonvolatile memory.

7. The operating method of claim 2 , wherein the second period by which the current weighted time is calculated is shorter than the first period by which the temperature is detected.

8. The operating method of claim 1 , wherein the temperature is detected using an internal temperature sensor of the storage device or an external temperature sensor of the storage device.

9. The operating method of claim 1 , further comprising:
writing the data to the nonvolatile memory; and
registering a weighted time which is associated with the data written to the nonvolatile memory as a weighted time stamp of the data.

10. The operating method of claim 9 , further comprises:
calculating a difference between the weighted time stamp of the data and the current weighted time of the data, wherein the read voltage level is adjusted based on the calculated difference.

11. The operating method of claim 9 , further comprising:
if power is off and then supplied,
detecting an optimal read voltage level for reading the data;
calculating a difference between the optimal read voltage level and a default read voltage level;
and calculating a weighted time using the difference, wherein the weighted time is used as the previous weighted time.

12. The operating method of claim 9 , wherein the weighted time stamp includes a physical address information of the nonvolatile memory where the data is written.

13. A storage device comprising:
a temperature sensor;
a nonvolatile memory; and
a memory controller configured to control the nonvolatile memory,
wherein the memory controller is configured to calculate a current weighted time based on a variation in a temperature detected via the temperature sensor and reads data from the nonvolatile memory using a read voltage level adjusted according to the current weighted time, and
wherein the memory controller is further configured to periodically detects the temperature at a first period, and to periodically calculates the current weighted time at a second period based on the detected temperature.

14. The storage device of claim 13 , further comprising:
a random access memory,
wherein the memory controller is further configured to periodically stores the detected temperature in the random access memory.

15. The storage device of claim 14 , wherein the memory controller writes the data to the nonvolatile memory, reads a weighted time from the random access memory, and registers the weighted time as a weighted time stamp of the data.

16. The storage device of claim 15 , wherein the weighted time stamp of the data written to the nonvolatile memory are managed in the random access memory as a time stamp table.

17. The storage device of claim 16 , wherein the time stamp table is further stored in the nonvolatile memory.

18. The storage device of claim 15 , wherein the memory controller further configured to:
read the current weighted time from the random access memory; and
calculate a difference between the weighted time stamp and the current weighted time,
wherein the read voltage level is adjusted according to the calculated difference.

19. The storage device of claim 13 , wherein the nonvolatile memory includes vertically stacked memory cells.

20. The storage device of claim 19 , wherein each memory cell is a charge trap type.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Sejeong
• Kim Kyungryun
• Kim Nam-Ho

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title