Gate driving circuit and display apparatus including the same

Patent metadata

Field	Value
Publication number	US-9343030-B2
Application number	US-84064210-A
Country	US
Kind code	B2
Filing date	Jul 21, 2010
Priority date	Dec 29, 2009
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A gate driving circuit includes N stages (where N is a natural number greater than or equal to 2). The N stages are cascaded, and each of the N stages has a gate line connected thereto. A first stage group includes k stages of the N stages (where k is a natural number less than N), and the first stage group outputs a first output signal in response to a start signal. A second stage group (including N−k stages) generates a second output signal in response to the first output signal and outputs the second output signal to a corresponding gate line. The first stage group includes a first buffer and a second buffer, each of which receives the start signal. A size of the first buffer is smaller than a size of the second buffer.

First claim

What is claimed is:

1. A gate driving circuit comprising:
N stages, where N is a natural number greater than or equal to 3, the N stages are cascaded, and each of the N stages has a respective gate line connected and corresponding thereto;
a first stage group including k stages of the N stages, where k is a natural number less than N, and which outputs first output signals in response to a same start signal; and
a second stage group including N-k stages, and which generates second output signals in response to the corresponding first output signals from the first stage group and outputs the second output signal to a corresponding gate line, wherein
the first stage group comprises first buffers which receive the start signal and the second stage group comprises second buffers which receive the first output signals, and
a size of the first buffer is smaller than a size of the second buffer,
wherein respective first buffers are diode-connected to respective first terminals of the k stages which receive the same start signal, and
respective second buffers are diode-connected to respective second terminals of the N-k stages which receive the first output signals.

2. The gate driving circuit of claim 1 , wherein the first stage group comprises:
a first stage;
a second stage; and
a third stage, and
the second stage group comprises fourth through N-th stages.

3. The gate driving circuit of claim 2 , wherein
the first buffer is included in the second stage or in the third stage, and
the second buffer is included in one of the fourth stage to the Nth stage of the second stage group.

4. The gate driving circuit of claim 2 , wherein the size of the first buffer is smaller than the size of the second buffer by about 35 percent.

5. The gate driving circuit of claim 2 , further comprising a dummy stage which applies a dummy output signal to the first stage group and the second stage group to lower the first output signal and the second output signal to a level of a gate-off voltage.

6. The gate driving circuit of claim 5 , wherein the first stage group and the second stage group each comprises:
a voltage output part which applies a clock signal to the gate lines as a gate voltage in response to one of the start signal and an output signal outputted from a previous stage;
an output driving part which receives one of the start signal and the output signal outputted from the previous stage to drive the voltage output part;
a holding part which holds the gate lines at the gate-off voltage; and
a discharge part disposed at an end portion of the gate lines to discharge the gate lines to the gate-off voltage in response to the gate voltage outputted from the voltage output part.

7. The gate driving circuit of claim 6 , wherein the voltage output part comprises:
a pull-up transistor comprising:
a control electrode which receives one of the start signal and the output signal from the previous stage;
an input electrode which receives the clock signal; and
an output electrode connected to the gate line; and
a pull-down transistor comprising:
a control electrode which receives the output signal from a next stage;
an input electrode connected to the output electrode of the pull-up transistor; and
an output electrode connected to an input terminal which receives an off voltage.

8. The gate driving circuit of claim 7 , wherein the first buffer and the second buffer each comprises a transistor comprising:
an input electrode and a control electrode which receive the output signal from the previous stage; and
an output electrode connected to the control electrode of the pull-up transistor.

9. The gate driving circuit of claim 6 , wherein the clock signal comprises:
a first clock signal, a second clock signal and a third clock signal, each of which is repeatedly turned on and off at different time delay periods; and
a fourth clock signal, a fifth clock signal and a sixth clock signal, each of which is repeatedly turned on and off and has a different phase from each of the first clock signal, the second clock signal and the third clock signal, respectively.

10. The gate driving circuit of claim 9 , wherein
the different time delay periods include 1 horizontal period, and
the phase difference is about 180 degrees.

11. A display apparatus comprising:
pixels arranged in a matrix;
gate lines which apply gate signals to the pixels;
data lines which apply data signals to the pixels;
a gate driver connected to the gate lines and which generates the gate signal based on at least one clock signal;
a data driver connected to the data lines and which generates the data signal; and
a controller which controls an operation of the gate driver and the data driver, wherein
the gate driver comprises:
a first stage group comprising a first stage, a second stage and a third stage, the first stage, the second and the third stage each of which receive a same start signal, and which respectively generate first gate signals and respectively applies the first gate signals to corresponding gate lines connected to the corresponding first stage, second and third stage, respectively; and
a second stage group which receives the first gate signals outputted from the first stage group, generates second gate signals and applies the first gate signals to corresponding gate lines, the second stage group comprises fourth through N-th stages, where N is a natural number,
the first stage group comprises first buffers which receive the start signal and the second stage group comprises second buffers which receive the first gate signals, and
a size of the first buffer is smaller than a size of the second buffer,
wherein respective first buffers are diode-connected to respective first terminals of the first, second and third stages which receive the same start signal, and
respective second buffers are diode-connected to respective second terminals of the fourth through N-stages which receive the first gate signals.

12. The display apparatus of claim 11 , wherein the first buffer is included in the second stage and the third stage, respectively,
the second buffer is included in one of the fourth stage to the Nth stage of the second stage group, and
the size of the first buffer is smaller than the size of the second buffer by about 35 percent.

13. The display apparatus of claim 12 , wherein the first stage group and the second stage group each comprises:
a voltage output part which applies a clock signal to the gate lines as a gate signal in response to one of the start signal and a signal outputted from a previous stage;
an output driving part which receives the one of the start signal and the signal outputted from the previous stage and drives the voltage output part;
a holding part which holds the gate lines at a gate-off voltage; and
a discharge part disposed at an end portion of the gate lines to discharge the gate lines to the gate-off voltage in response to the gate voltage outputted from the voltage output part.

14. The display apparatus of claim 11 , wherein the clock signal comprises:
a first clock signal, a second clock signal and a third clock signal, each of which is repeatedly turned on and off at different time delay periods; and
a fourth clock signal, a fifth clock signal and a sixth clock signal, each of which is repeatedly turned on and off and has a different phase from each of the first clock signal, the second clock signal and the third clock signal, respectively,
wherein the time delay period includes 1 horizontal period and the phase difference is about 180 degrees.

15. A display app

Assignees

• Kim Hyuk-Jin
• Park Kyung-Ho
• No Sang Yong
• Cho Youngje
• Choi Kook Hyun
• Kim Yongjo
• Kim Sung Hoon
• Kim Hyo-Seop
• Samsung Display Co Ltd

Inventors

• Kim Hyuk-Jin
• Park Kyung-Ho
• No Sang Yong
• Cho Youngje
• Choi Kook Hyun
• Kim Yongjo
• Kim Sung Hoon
• Kim Hyo-Seop

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0417

  Special arrangements specific to the use of low carrier mobility technology · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• H03K19/00

  Logic circuits, i.e. having at least two inputs acting on one output (circuits for computer systems using fuzzy logic G06N7/02); Inverting circuits · CPC title