Data storage system and method of operating data storage system

Patent metadata

Field	Value
Publication number	US-9342447-B2
Application number	US-201313957901-A
Country	US
Kind code	B2
Filing date	Aug 2, 2013
Priority date	Aug 7, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A method of operating a data storage device includes providing a memory cell array that includes a first word line, a second word line and a buffer configured to store second data to be programmed into the second word line, reading the second data from the buffer, and programming first data into the first word line. A programming condition of the first data being is changed based on the second data read from the buffer.

First claim

What is claimed is:

1. A method of operating a data storage device, the method comprising:
providing a memory cell array, comprising a first word line and a second word line, and a buffer configured to store second data to be programmed into the second word line;
reading the second data from the buffer; and
programming first data into memory cells connected to the first word line, a programming condition of the first data being changed based on the second data read from the buffer, wherein programming the first data into the first word line comprises:
sensing first memory cells connected to the first word line that belong to a first partial distribution included in a first threshold voltage distribution, and sensing second memory cells connected to the first word line that belong to a second partial distribution included in the first threshold voltage distribution;
selecting at least one second memory cell having a high error rate from the sensed second memory cells based on the second data read from the buffer; and
shifting the selected at least one second memory cell having the high error rate to a second threshold voltage distribution which is different from the first threshold voltage distribution.

2. The method of claim 1 , further comprising:
programming the second data into the second word line after the programming of the first data into the first word line.

3. The method of claim 1 , wherein the programming condition of the first data is changed by changing a program voltage for programming the first data.

4. The method of claim 3 , wherein the program voltage is an incremental step pulse programming (ISPP) voltage which is increased step by step from a start voltage by a delta voltage in each program loop.

5. The method of claim 4 , wherein the programming condition of the first data is changed by changing the delta voltage or the start voltage based on the second data.

6. The method of claim 1 , wherein the programming condition is changed by changing a verify voltage.

7. The method of claim 1 ,
wherein the first partial distribution and the second partial distribution included in the first threshold voltage distribution do not overlap each other.

8. The method of claim 7 , wherein programming of the first data into the first word line further comprises:
shifting the first memory cells belonging to the first partial distribution to the second threshold voltage distribution, regardless of the second data.

9. The method of claim 7 , wherein in sensing whether the memory cells connected to the first word line belong to the first partial distribution or the second partial distribution comprises comparing threshold voltages of the memory cells with a first reference voltage and a second reference voltage which are different from each other, wherein memory cells having threshold voltages greater than the first reference voltage correspond to the first partial distribution, and memory cells having threshold voltages between the first reference voltage and the second reference voltage correspond to the second partial distribution.

10. The method of claim 7 , wherein A % of the memory cells corresponding to the first partial distribution are shifted to correspond to the second threshold voltage distribution, and B % of the memory cells corresponding to the second partial distribution are shifted to correspond to the second threshold voltage distribution, where 0<A≦100, 0<B≦100, and B<A.

11. A method of operating a data storage device, the method comprising:
sensing whether a plurality of memory cells belong to a first partial distribution or a second partial distribution included in a first threshold voltage distribution, wherein the first partial distribution and the second partial distribution do not overlap each other; and
shifting A % of a plurality of memory cells, included in the first partial distribution, to correspond to a second threshold voltage distribution which is different from the first threshold voltage distribution, and shifting B % of a plurality of memory cells included in the second partial distribution, to correspond to the second threshold voltage distribution, where 0<A≦100, 0<B≦100, and B<A.

12. The method of claim 11 , wherein the first threshold voltage distribution is an erase state distribution, and the second threshold voltage distribution is a program state distribution.

13. The method of claim 11 , wherein the sensing of whether the memory cells belong to the first partial distribution or the second partial distribution comprises comparing threshold voltages of the memory cells with a first reference voltage and a second reference voltage which are different from each other.

14. The method of claim 13 , wherein memory cells having threshold voltages greater than the first reference voltage correspond to the first partial distribution.

15. The method of claim 13 , wherein memory cells having threshold voltages between the first reference voltage and the second reference voltage correspond to the second partial distribution.

16. The method of claim 11 , wherein all of the memory cells corresponding to the first partial distribution are shifted to correspond to the second threshold voltage distribution, and some of the memory cells corresponding to the second partial distribution are shifted to correspond to the second threshold voltage distribution.

17. The method of claim 11 , further comprising:
selecting memory cells having high error rates from the memory cells corresponding to the second partial distribution after the sensing of whether the memory cells belong to the first partial distribution or the second partial distribution.

18. The method of claim 17 , wherein the memory cells having the high error rates are selected based on data which is to be programmed into memory cells surrounding each of the memory cells corresponding to the second partial distribution.

19. The method of claim 18 , wherein the surrounding memory cells are memory cells connected to a word line above each of the memory cells corresponding to the second partial distribution.

20. The method of claim 18 , wherein the surrounding memory cells are memory cells connected to a same word line as each of the memory cells corresponding to the second partial distribution.

21. The method of claim 18 , wherein the surrounding memory cells are memory cells connected to a same bit line as each of the memory cells corresponding to the second partial distribution.

22. The method of claim 17 , further comprising:
selecting memory cells having high error rates from the memory cells corresponding to the first partial distribution.

23. A method of operating a data storage device, the method comprising:
sensing whether a plurality of memory cells belong to a first partial distribution or a second partial distribution, wherein the first partial distribution and the second partial distribution are included in a first threshold voltage distribution and do not overlap each other;
selecting memory cells having high error rates from a plurality of memory cells corresponding to the second partial distribution; and
shifting the selected memory cells having the high error rates to correspond to a second threshold voltage distribution which is different from the first threshold voltage distribution.

24. The method of claim 23 , wherein the memory cells having the high error rates are selected based on data which is to be programmed into memor

Assignees

• Kim Kyung-Ryun
• Yoon Sang-Yong
• Song Ki-Whan
• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Ryun
• Yoon Sang-Yong
• Song Ki-Whan

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title