Secure error handling

Patent metadata

Field	Value
Publication number	US-9342394-B2
Application number	US-201113997301-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
an operating system; and
a platform comprising a basic input/output system and a hardware processor, the hardware processor comprising an error register;
wherein the operating system is to write in a secure manner to the error register via the basic input/output system, and the basic input/output system is to enable or disable error signaling between the operating system and the hardware processor based on support in the hardware processor for a code coverage error injection capability.

2. The apparatus of claim 1 , the platform further comprising system management mode functionality, wherein the operating system is to write to the error register in a secure manner via the system management mode functionality.

3. The apparatus of claim 2 , wherein the basic input/output system comprises the system management mode functionality.

4. The apparatus of claim 1 , wherein the operating system is to write in a secure manner to the error register via platform firmware.

5. The apparatus of claim 1 , wherein the error register comprises at least one of a machine check architecture register and an error signaling register.

6. The apparatus of claim 1 , wherein the error register is enabled and/or disabled via the platform.

7. The apparatus of claim 1 , wherein the error register is a machine check architecture register that is enabled and/or disabled only by the platform.

8. The apparatus of claim 1 , wherein the platform is to control error signaling between the operating system and the hardware processor.

9. The apparatus of claim 1 , wherein the error register is a machine check architecture register that is controlled by the platform, and the hardware processor further comprises an error signaling register that is controlled by the platform.

10. The apparatus of claim 1 , wherein the operating system is to write to the error register via the platform.

11. The apparatus of claim 1 , wherein error injection is implemented via the platform.

12. A method comprising:
enabling or disabling error signaling between an operating system and a hardware processor based on support in the hardware processor for a code coverage error injection capability; and
writing to an error register in the hardware processor from the Operating System via the basic input/output system in a secure manner.

13. The method of claim 12 , further comprising writing in a secure manner to the error register included in the hardware processor from the operating system via system management mode functionality included in the platform.

14. The method of claim 13 , wherein the basic input/output system of the platform comprises the system management mode functionality.

15. The method of claim 12 , further comprising writing from the operating system to the error register in a secure manner via platform firmware.

16. The method of claim 12 , wherein the error register comprises at least one of a machine check architecture register and an error signaling register.

17. The method of claim 12 , further comprising enabling and/or disabling the error register via the platform.

18. The method of claim 12 , wherein the error register is a machine check architecture register, further comprising enabling and/or disabling the machine check architecture register only by the platform.

19. The method of claim 12 , further comprising controlling error signaling between the operating system and the processor via the platform.

20. The method of claim 12 , wherein the error register is a machine check architecture register, further comprising controlling the machine check architecture register and an error signaling register in the hardware processor by the platform.

21. The method of claim 12 , further comprising writing from the operating system to the error register via the platform.

22. The method of claim 12 , further comprising injecting one or more error via the platform.

Assignees

• Nachimuthu Murugasamy
• Kumar Mohan J
• Yigzaw Theodros
• Vargas Jose A
• Kuramkote Rajender
• Intel Corp

Inventors

• Nachimuthu Murugasamy
• Kumar Mohan J
• Yigzaw Theodros
• Vargas Jose A
• Kuramkote Rajender

Classifications

• G06F11/3698 Primary

  Environments for analysis, debugging or testing of software · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F21/57

  Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title

• G06F11/3664

  Physics · mapped topic

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title