Optimization of instructions to reduce memory access violations

Patent metadata

Field	Value
Publication number	US-9342284-B2
Application number	US-201314040077-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Mechanisms for reducing memory access violations are disclosed. Sets of instructions may be identified and the identified sets of instructions may be re-translated or optimized to generate other sets of instructions. Execution of the other sets of instructions is analyzed to determine whether additional memory access violations occur. When additional memory access violations occur, further sets of instructions may be generated or re-translation/optimization of instructions may be disabled.

First claim

What is claimed is:

1. An apparatus comprising:
a memory module to store a plurality of instructions of an application;
a processor communicatively coupled to the memory, the processor to:
identify a first set of instructions from the plurality of instructions, wherein execution of the first set of instructions is to cause a first out-of-order execution fault;
generate a second set of instructions comprising a first instruction and a second instruction from the first set of instructions, wherein the first instruction and the second instruction have a different order in the second set of instruction than in the first set of instructions;
replace the first set of instructions with the second set of instructions at a same location in the plurality of instructions as the first set of instructions;
determine that the order of the first instruction in the second set of instructions is to cause a second out-of-order execution fault;
generate a third set of instruction comprising the second set of instructions, wherein the first instruction in the second set of instructions is reordered to be in the same order as the first instruction was in the first instruction set; and
replace the second set of instructions with the third set of instructions.

2. The apparatus of claim 1 , wherein the processor identifies the first set of instructions to cause the first out-of-order execution fault by determining that a first instruction from the first set of instructions and a second instruction from the first set of instructions both access a same memory location and access mutually exclusive portions of the same memory location.

3. The apparatus of claim 1 , wherein the second set of instructions comprises at least one vector instruction.

4. The apparatus of claim 1 , wherein the processor identifies the first set of instructions to cause the first out-of-order execution fault by determining that a first instruction from the first set of instructions and a second instruction from the first set of instructions both access a same memory location and both access a same portion of the same memory location.

5. The apparatus of claim 1 , wherein the processor is to:
determine a first memory address for a first memory location of a first instruction of the second set of instructions and a second memory address for a second memory location of a second instruction of the second set of instructions; and
determine whether the first address matches the second address.

6. The apparatus of claim 1 , wherein the processor is further configured to:
determine whether execution of the third set of instructions causes a third out-of-order execution fault; and
when the execution of the third set of instructions causes the third out-of-order execution fault, replace the third set of instructions with the first set of instructions.

7. The apparatus of claim 1 , wherein the processor generates the third set of instructions when a total number of out-of-order execution faults is less than or equal to a threshold.

8. The apparatus of claim 1 , wherein:
the first set of instructions is atomic,
the second set of instructions is atomic, and
the third set of instructions is atomic.

9. A method comprising:
identifying a first set of instructions from a plurality of instructions, wherein execution of the first set of instructions causes a first out-of-order execution fault;
generating a second set of instructions comprising a first instruction and a second instruction from the first set of instructions, wherein the first instruction and the second instruction have a different order in the second set of instruction than in the first set of instructions;
replacing the first set of instructions with the second set of instructions at a same location in the plurality of instructions as the first set of instructions;
determining that the order of the first instruction in the second set of instructions causes a second out-of-order execution fault;
generate a third set of instructions comprising the second set of instructions, wherein the first instruction in the second set of instructions is reordered to be in the same order as the first instruction was in the first instruction set; and
replacing the second set of instructions with the third set of instructions.

10. The method of claim 9 , wherein identifying the first set of instructions causing the first out-of-order execution fault comprises determining that a first instruction from the first set of instructions and a second instruction from the first set of instructions both access a same memory location and access mutually exclusive portions of the same memory location.

11. The method of claim 9 , wherein the second set of instructions comprises at least one vector instruction.

12. The method of claim 9 , wherein identifying the first set of instructions causing the first out-of-order execution fault comprises determining that a first instruction from the first set of instructions and a second instruction from the first set of instructions both access a same memory location and both access a same portion of the same memory location.

13. The method of claim 9 , further comprising:
determining a first memory address for a first memory location of a first instruction of the second set of instructions and a second memory address for a second memory location of a second instruction of the second set of instructions; and
determining whether the first address matches the second address.

14. The method of claim 9 , further comprising:
determining whether execution of the third set of instructions causes a third out-of-order execution fault; and
when the execution of the third set of instructions causes the third out-of-order execution fault, replacing the third set of instructions with the first set of instructions.

15. The method of claim 9 , wherein the third set of instructions is generated when a total number of out-of-order execution faults is less than or equal to a threshold.

16. The method of claim 9 , wherein:
the first set of instructions is atomic,
the second set of instructions is atomic, and
the third set of instructions is atomic.

17. A system comprising:
a processor communicatively coupled to a memory, the processor to:
identify a first set of instructions from a plurality of instructions in the memory, wherein execution of the first set of instructions is to cause a first out-of-order execution fault;
generate a second set of instructions comprising a first instruction and a second instruction from the first set of instructions, wherein the first instruction and the second instruction have a different order in the second set of instruction than in the first set of instructions;
replace the first set of instructions with the second set of instructions at a same location in the plurality of instructions as the first set of instructions;
determine that the order of the first instruction in the second set of instructions is to cause a second out-of-order execution fault;
generate a third set of instructions comprising the second set of instructions, wherein the first instruction in the second set of instructions is reordered to be in the same order as the first instruction was in the first instruction set; and
replace the second set of instructions with the third set of instructions.

18. The system of claim 17 , wherein the processor identifies the first set of instructions to cause the first out-of-order execution fault by determining that a first instruction from the first set of instructions and a seco

Assignees

• Hassanein Wessam M
• Kanhere Abhay S
• Caprioli Paul
• Intel Corp

Inventors

• Hassanein Wessam M
• Kanhere Abhay S
• Caprioli Paul

Classifications

• G06F11/3604

  Analysis of software for verifying properties of programs (testing of software G06F11/3668) · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F8/4442 Primary

  Reducing the number of cache misses; Data prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/45516

  Runtime code conversion or optimisation · CPC title