Accelerated thermal mitigation for multi-core processors

Patent metadata

Field	Value
Publication number	US-9342135-B2
Application number	US-201314052191-A
Country	US
Kind code	B2
Filing date	Oct 11, 2013
Priority date	Oct 11, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A temperature sensor may sense the temperature of a multi-core processor. In response to the temperature of the multi-core processor exceeding a temperature threshold for the multi-core processor, one or more busy processor cores of the multi-core processor may be power collapsed without reducing clock speed of the multi-core processor.

First claim

The invention claimed is:

1. A method for thermally mitigating a multi-core processor, comprising:
power collapsing sets of one or more busy processor cores of a multi-core processor on a rotating basis amongst cores of the multi-core processor without reducing clock speed of the multi-core processor in response to instances of a temperature of the multi-core processor exceeding a temperature threshold, including determining an elapsed time for the temperature of the multi-core processor to fall below the temperature threshold responsive to power collapsing each set of the one or more busy processor cores to determine a set of the one or more busy processor cores that, when power collapsed, produces a shortest elapsed time for the temperature of the multi-core processor to fall below the temperature threshold; and
in response to the temperature of the multi-core processor exceeding the temperature threshold at a subsequent instance, power collapsing the set of the one or more busy processor cores that, when power collapsed, produces the shortest elapsed time for the temperature of the multi-core processor to fall below the temperature threshold.

2. The method of claim 1 , further comprising:
determining the set of one or more busy processor cores of the multi-core processor to power collapse based on power leakage characteristics of the one or more busy processor cores of the multi-core processor.

3. The method of claim 1 , further comprising:
determining the set of one or more busy processor cores of the multi-core processor to power collapse based on a cool down speed of the set of one or more busy processor cores of the multi-core processor.

4. The method of claim 1 , wherein the temperature threshold is less than an emergency temperature threshold.

5. The method of claim 1 , wherein power collapsing the set of one or more busy processor cores of the multi-core processor further comprises:
determining, by a sequencer, not to schedule instructions for the set of one or more busy processor cores to process.

6. The method of claim 1 , wherein power collapsing the set of one or more busy processor cores further comprises:
power collapsing one or more caches associated with the set of one or more busy processor cores.

7. The method of claim 1 , further comprising:
sensing the temperature of the multi-core processor.

8. An apparatus comprising:
a multi-core processor; and
a power control module configured to:
power collapse sets of one or more busy processor cores of the multi-core processor on a rotating basis amongst cores of the multi-core processor without reducing clock speed of the multi-core processor in response to instances of a temperature of the multi-core processor exceeding a temperature threshold, including determining an elapsed time for the temperature of the multi-core processor to fall below the temperature threshold responsive to power collapsing each set of the one or more busy processor cores to determine a set of the one or more busy processor cores that, when power collapsed, produces a shortest elapsed time for the temperature of the multi-core processor to fall below the temperature threshold; and
in response to the temperature of the multi-core processor exceeding the temperature threshold at a subsequent instance, power collapse the set of the one or more busy processor cores that, when power collapsed, produces the shortest elapsed time for the temperature of the multi-core processor to fall below the temperature threshold.

9. The apparatus of claim 8 , wherein the power control module is further configured to determine the set of one or more busy processor cores of the multi-core processor to power collapse based on power leakage characteristics of the set of one or more busy processor cores of the multi-core processor.

10. The apparatus of claim 8 , wherein the power control module is further configured to determine the set of one or more busy processor cores of the multi-core processor to power collapse based on a cool down speed of the set of one or more busy processor cores of the multi-core processor.

11. The apparatus of claim 8 , wherein the temperature threshold is less than an emergency temperature threshold.

12. The apparatus of claim 8 , further comprising:
a sequencer configured to determine not to schedule instructions for the set of one or more busy processor cores to process.

13. The apparatus of claim 8 , wherein power collapse the set of one or more busy processor cores further comprises:
power collapse one or more caches associated with the set of one or more busy processor cores.

14. The apparatus of claim 8 , further comprising:
a temperature sensor configured to sense the temperature of the multi-core processor.

15. An apparatus comprising:
means for power collapsing sets of one or more busy processor cores of a multi-core processor on a rotating basis amongst cores of the multi-core processor without reducing clock speed of the multi-core processor in response to instances of a temperature of the multi-core processor exceeding a temperature threshold, including determining an elapsed time for the temperature of the multi-core processor to fall below the temperature threshold responsive to power collapsing each set of the one or more busy processor cores to determine a set of the one or more busy processor cores that, when power collapsed, produces a shortest elapsed time for the temperature of the multi-core processor to fall below the temperature threshold; and
means for power collapsing the set of the one or more busy processor cores that, when power collapsed, produces the shortest elapsed time for the temperature of the multi-core processor to fall below the temperature threshold, in response to the temperature of the multi-core processor exceeding the temperature threshold at a subsequent instance.

16. The apparatus of claim 15 , further comprising:
means for determining the set of one or more busy processor cores of the multi-core processor to power collapse based on power leakage characteristics of the set of first one or more busy processor cores of the multi-core processor.

17. The apparatus of claim 15 , further comprising:
means for determining the set of first one or more busy processor cores of the multi-core processor to power collapse based on a cool down speed of the set of one or more busy processor cores of the multi-core processor.

18. The apparatus of claim 15 , wherein the temperature threshold is less than an emergency temperature threshold.

19. The apparatus of claim 15 , wherein the means for power collapsing the set of one or more busy processor cores of the multi-core processor further comprises:
means for determining not to schedule instructions for the set of one or more busy processor cores to process.

20. The apparatus of claim 15 , wherein the means for power collapsing the set of one or more busy processor cores further comprises:
means for power collapsing one or more caches associated with the set of one or more busy processor cores.

21. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more a programmable processors to:
power collapse sets of one or more busy processor cores of a multi-core processor on a rotating basis amongst cores of the multi-core processor without reducing clock speed of the multi-core processor in response to instances of a temperature of the multi-core processor exceeding a temperature threshold, including dete

Assignees

• Qualcomm Inc

Inventors

• Brackman David Samuel
• Sethi Sumeet Singh

Classifications

• Y02B60/1275

  Cross-Sectional Technologies · mapped topic

• Y02B60/1239

  Cross-Sectional Technologies · mapped topic

• G06F1/206 Primary

  comprising thermal management · CPC title

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• G06F1/3243

  Power saving in microcontroller unit · CPC title