Liquid crystal display

Patent metadata

Field	Value
Publication number	US-9341907-B2
Application number	US-201514802778-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Oct 29, 2010
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A liquid crystal display includes: a first substrate, a second substrate facing the first substrate, a liquid crystal layer interposed between the first substrate and the second substrate and including liquid crystal molecules, a gate line positioned on the first substrate, a data line positioned on the first substrate and crossing the gate line, a first thin film transistor and a second thin film transistor connected to the gate line and the data line, a third thin film transistor connected to the gate line and the second thin film transistor, a reference voltage line connected to the third thin film transistor, and a pixel electrode including a first subpixel electrode connected to the first thin film transistor and a second subpixel electrode connected to the second thin film transistor.

First claim

What is claimed is:

1. A liquid crystal display, comprising:
a first substrate;
a second substrate facing the first substrate;
a liquid crystal layer interposed between the first substrate and the second substrate and including liquid crystal molecules;
a gate line disposed on the first substrate;
a data line disposed on the first substrate and crossing the gate line;
a first thin film transistor and a second thin film transistor connected to the gate line and the data line;
a third thin film transistor connected to the gate line and the second thin film transistor;
a reference voltage line connected to the third thin film transistor; and
a pixel electrode including a first subpixel electrode connected to the first thin film transistor and a second subpixel electrode connected to both the second thin film transistor and the third thin transistor,
wherein a drain electrode of the second thin film transistor has a single body with a source electrode of the third thin film transistor,
wherein the reference voltage line comprises an output terminal of the third thin film transistor.

2. The liquid crystal display of claim 1 , wherein:
the second thin film transistor is connected to the second subpixel electrode and the third thin film transistor.

3. The liquid crystal display of claim 2 , wherein:
a voltage applied to the second subpixel electrode is lower than a voltage applied to the first subpixel electrode.

4. The liquid crystal display of claim 3 , wherein:
an area of the second subpixel electrode is equal to or larger than an area of the first subpixel electrode.

5. The liquid crystal display of claim 4 , wherein:
a ratio of the area of the first subpixel electrode and the area of the second subpixel electrode is in the range of about 1:1 to 1:2.

6. The liquid crystal display of claim 5 , wherein:
when a ratio of a channel width versus a channel length of the second thin film transistor is called a first channel ratio and a ratio of a channel width versus a channel length of the third thin film transistor is called a second channel ratio,
a percentage of the first channel ratio with respect to the sum of the first channel ratio and the second channel ratio is in the range of about 70% to 80%.

7. The liquid crystal display of claim 6 , wherein:
a reference voltage applied through the reference voltage line is in the range of about 8V to 11V and a common voltage applied to a common electrode disposed on the second substrate is about 7V.

8. The liquid crystal display of claim 7 , wherein:
the reference voltage includes a swing signal.

9. The liquid crystal display of claim 8 , wherein:
the reference voltage includes a signal having a duty ratio which is swung in the range of about 50% to 80%.

10. The liquid crystal display of claim 3 , wherein:
the pixel electrode includes a first side parallel to the gate line and a second side parallel to the data line,
wherein a length of the first side is longer than that of the second side.

11. The liquid crystal display of claim 10 , wherein:
the first subpixel electrode and the second subpixel electrode each includes a cross-shaped stem having a horizontal stem and a vertical stem crossing the horizontal stem, and
a plurality of minute branches extending from the cross-shaped stem.

12. The liquid crystal display of claim 11 , wherein:
the first subpixel electrode and the second subpixel electrode each includes a plurality of subregions having the plurality of minute branches extended toward different directions from the cross-shaped stem.

13. The liquid crystal display of claim 12 , wherein:
the reference voltage line includes two vertical portions parallel to the data line and a horizontal portion connecting the vertical portions with each other.

14. The liquid crystal display of claim 13 , wherein:
the vertical portion of the reference voltage line is disposed between the pixel electrode and the data line and the horizontal portion of the reference voltage line is disposed between the pixel electrode and the gate line.

15. The liquid crystal display of claim 13 , further comprising:
a light blocking unit disposed below the vertical portion of the reference voltage line and formed on a same layer as the gate line.

16. The liquid crystal display of claim 15 , further comprising:
a shielding electrode disposed on a same layer as the pixel electrode and overlapping the gate line.

17. The liquid crystal display of claim 12 , wherein the reference voltage line extends along an extending direction of the vertical stem and overlaps the vertical stem.

18. The liquid crystal display of claim 3 ,
wherein each of the first subpixel electrode and the second subpixel electrode includes a first cutout, the common electrode includes a second cutout, and the first cutout and the second cutout arrange alternately.

19. The liquid crystal display of claim 3 , wherein:
the pixel electrode includes a first side parallel to the gate line and a second side parallel to the data line,
wherein a length of the second side is longer than that of the first side.

20. The liquid crystal display of claim 1 , wherein:
the gate line transfers a gate signal and gate signals applied to control terminals of the first thin film transistor, the second thin film transistor, and the third thin film transistor are simultaneously transferred.

21. The liquid crystal display of claim 1 , wherein:
the liquid crystal molecules are vertically aligned while an electric field is not applied.

22. The liquid crystal display of claim 1 , further comprising:
a shielding electrode line disposed along a direction which the data line is extended, wherein the shielding electrode line includes a shielding electrode protruded to overlap the gate line.

23. The liquid crystal display of claim 22 , wherein:
the shielding electrode is separated from the second subpixel electrode.

24. The liquid crystal display of claim 1 , wherein:
a voltage applied to the second subpixel electrode is lower than a voltage applied to the first subpixel electrode.

25. The liquid crystal display of claim 24 , wherein:
the second thin film transistor is connected to the second subpixel electrode and the third thin film transistor.

26. The liquid crystal display of claim 25 , wherein:
an area of the second subpixel electrode is equal to or larger than an area of the first subpixel electrode.

27. The liquid crystal display of claim 26 , wherein:
when a ratio of a channel width versus a channel length of the second thin film transistor is called a first channel ratio and a ratio of a channel width versus a channel length of the third thin film transistor is called a second channel ratio,
a percentage of the first channel ratio with respect to the sum of the first channel ratio and the second channel ratio is in the range of 70% to 80%.

28. The liquid crystal display of claim 27 , wherein:
the gate line transfers a gate signal and gate signals applied to control terminals of the first thin film transistor, the second thin film transistor, and the third thin film transistor are simultaneously transferred.

29. The liquid crystal display of claim 28 , wherein:
the pixel electrode includes a first side parallel to the gate line and a second side parallel to the data line,
wherein a length of the fi

Assignees

• Samsung Display Co Ltd
• Samsung Display Co Ltd

Inventors

• Kim Su-Jeong
• Shin Ki-Chul
• Kim Hoon
• Kim Hyung-Guel
• Yeom Joo-Seok
• Song Jae-Jin
• Oh Ho-Kil
• Kim Yoon-Jang
• Jung Jae-Hoon
• Jung Kwang-Chul

Classifications

• G02F1/134336

  Matrix · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F2001/134345

  Physics · mapped topic

• G02F1/13624 Primary

  having more than one switching element per pixel · CPC title

• G09G2320/028

  by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction · CPC title