Method and device for establishing a fault in connecting lines between a central unit and a plurality of electronic components which are independent of one another

US9341666B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9341666-B2
Application numberUS-201214360418-A
CountryUS
Kind codeB2
Filing dateNov 28, 2012
Priority dateNov 30, 2011
Publication dateMay 17, 2016
Grant dateMay 17, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for establishing at least one fault in connecting lines between electronic connection units and peripheral units, which are independent of one another, includes: outputting a start signal from the control unit to a first of the connection units, to start the establishment of the fault; applying a test signal to an interface of a first one of the connection units, the application of the test signal being monitored and/or controlled by a non-volatile first algorithm of the first connection unit; registering a cross-coupling of the test signal to an interface of a second connection unit and storing a fault value representing the cross-coupling in a first register, the registration and the storage of the fault value being monitored and/or controlled by a nonvolatile second algorithm of the second connection unit.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for establishing at least one test fault in connecting lines between a plurality of electronic connection units and a plurality of peripheral units, the peripheral units being independent from one another, the connection units being controlled by a volatile algorithm programmed into a control unit, and the connecting lines between the peripheral units and the connection units being each implemented with the aid of at least one two-wire line, the method comprising: outputting a start signal from the control unit to a first one of the connection units to start the establishment of the fault; applying a test signal to an interface of a first of the connection units, wherein the application of the test signal is at least one of monitored and controlled by a nonvolatile first algorithm programmed into the first connection unit; registering a cross-coupling of the test signal to an interface of a second connection unit and storing a fault value representing the cross-coupling in a first register, wherein the registration and storage of the fault value is at least one of monitored and controlled by a nonvolatile second algorithm programmed into the second connection unit; and reading out the at least one fault value by the control unit at least from the first register to establish the fault in the connecting lines between the first connection unit and the plurality of peripheral units. 2. The method as recited in claim 1 , further comprising: registering a cross-coupling of the test signal to a second interface of the first connection unit and storing a second fault value representing the cross-coupling in a second register, the registration of a cross-coupling of the test signal to the second interface of the first connection unit and the storage of the second fault value being monitored by the first algorithm. 3. The method as recited in claim 1 , further comprising: applying a further test signal to the interface of the second connection unit, the application of the further test signal being monitored by the second algorithm; and registering a cross-coupling of the further test signal to the first interface in the first connection unit and storing a third fault value representing the cross-coupling of the further test signal in a third register, the registration of the cross-coupling of the further test signal and the storage of the third fault value being at least one of monitored and controlled by the first algorithm. 4. The method as recited in claim 3 , further comprising: registering a cross-coupling of the further test signal to at least one second interface of the second connection unit and storing a fourth fault value representing the cross-coupling in a fourth register, the registration of the cross-coupling of the further test signal and the storage of the fourth fault value being at least one of monitored and controlled by the second algorithm. 5. The method as recited in claim 3 , wherein, prior to the step of applying the further test signal, a control signal is output by the first algorithm to the second algorithm to start the application of the further test signal by the second algorithm. 6. The method as recited in claim 2 , further comprising: registering a cross-coupling of the test signal to an interface of a third connection unit and storing a fifth fault value representing the cross-coupling of the test signal to the interface of the third connection unit in a fifth register, the registration of the cross-coupling of the test signal to the interface of the third connection unit and the storage of the fifth fault value being at least one of monitored and controlled by a nonvolatile third algorithm programmed into the third connection unit. 7. The method as recited in claim 2 , wherein a predefined duration elapses between the applying of the test signal and the registering of the cross-coupling of the test signal to the interface of the second connection unit. 8. The method as recited in claim 2 , wherein one of (i) the first register is a part of the second connection unit or (ii) the first register is a part of the control unit. 9. The method as recited in claim 2 , wherein the interfaces of the first and second connection units are configured as PSI5 interfaces. 10. The method as recited in claim 1 , wherein at least one of a short-circuit to a ground potential and a short-circuit to a supply voltage potential is registered as a cross-coupling of the test signal. 11. A non-transitory, computer-readable data storage medium storing a computer program having program codes which, when executed on a computer, performs a method for establishing at least one test fault in connecting lines between a plurality of electronic connection units and a plurality of peripheral units, the peripheral units being independent from one another, the connection units being controlled by a volatile algorithm programmed into a control unit, and the connecting lines between the peripheral units and the connection units being each implemented with the aid of at least one two-wire line, the method comprising: outputting a start signal from the control unit to a first one of the connection units to start the establishment of the fault; applying a test signal to an interface of a first of the connection units, wherein the application of the test signal is at least one of monitored and controlled by a nonvolatile first algorithm programmed into the first connection unit; registering a cross-coupling of the test signal to an interface of a second connection unit and storing a fault value representing the cross-coupling in a first register, wherein the registration and storage of the fault value is at least one of monitored and controlled by a nonvolatile second algorithm programmed into the second connection unit; and reading out the at least one fault value by the control unit at least from the first register to establish the fault in the connecting lines between the first connection unit and the plurality of peripheral units.

Assignees

Inventors

Classifications

  • G01D3/08Primary

    with provision for safeguarding the apparatus, e.g. against abnormal operation, against breakdown · CPC title

  • using microprocessors or computers · CPC title

  • G01R31/025Primary

    Physics · mapped topic

  • Testing for short-circuits, leakage current or ground faults · CPC title

  • Testing of lines, cables or conductors (testing of electric windings G01R31/72) · CPC title

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What does patent US9341666B2 cover?
A method for establishing at least one fault in connecting lines between electronic connection units and peripheral units, which are independent of one another, includes: outputting a start signal from the control unit to a first of the connection units, to start the establishment of the fault; applying a test signal to an interface of a first one of the connection units, the application of the…
Who is the assignee on this patent?
Weiss Timo, Siemss Matthias, Widmaier Jochen, and 2 more
What technology area does this patent fall under?
Primary CPC classification G01D3/08. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 17 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).