Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9337344-B2
Application number	US-201414272767-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	May 9, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a decrease in electrical characteristics caused by the decrease in the size, and a manufacturing method thereof. A source electrode layer and a drain electrode layer are formed on an upper surface of an oxide semiconductor layer. A side surface of the oxide semiconductor layer and a side surface of the source electrode layer are provided on the same surface and are electrically connected to a first wiring. Further, a side surface of the oxide semiconductor layer and a side surface of the drain electrode layer are provided on the same surface and are electrically connected to a second wiring.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first oxide semiconductor layer over an insulating surface;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode layer and a drain electrode layer over the second oxide semiconductor layer,
a third oxide semiconductor layer over the second oxide semiconductor layer,
a gate insulating film over the third oxide semiconductor layer;
a gate electrode layer over the gate insulating film; and
an insulating layer over the insulating surface, the source electrode layer, the drain electrode layer, and the gate electrode layer,
wherein a side surface of the source electrode layer and a first side surface of the second oxide semiconductor layer are in direct contact with a surface of a first wiring,
wherein a side surface of the drain electrode layer and a second side surface of the second oxide semiconductor layer are in direct contact with a surface of a second wiring,
wherein a first part of the third oxide semiconductor layer is in direct contact with the source electrode layer,
wherein a second part of the third oxide semiconductor layer is in direct contact with the drain electrode layer,
wherein a first opening that reaches a first part of the second oxide semiconductor layer and a part of the source electrode layer is located in the insulating layer,
wherein a second opening that reaches a second part of the second oxide semiconductor layer and a part of the drain electrode layer is located in the insulating layer,
wherein a third opening that reaches a part of the gate electrode layer is located in the insulating layer,
wherein the second oxide semiconductor layer and the source electrode layer are electrically connected to the first wiring in the first opening,
wherein the second oxide semiconductor layer and the drain electrode layer are electrically connected to the second wiring in the second opening, and
wherein the gate electrode layer is electrically connected to a third wiring in the third opening.

2. The semiconductor device according to claim 1 ,
wherein energy of a conduction band minimum of the first oxide semiconductor layer is closer to a vacuum level than energy of a conduction band minimum of the second oxide semiconductor layer by greater than or equal to 0.05 eV and less than or equal to 2 eV, and
wherein energy of a conduction band minimum of the third oxide semiconductor layer is closer to a vacuum level than the energy of the conduction band minimum of the second oxide semiconductor layer by greater than or equal to 0.05 eV and less than or equal to 2 eV.

3. The semiconductor device according to claim 1 ,
wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are each an In-M-Zn oxide,
wherein M is one of Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf, and
wherein an atomic ratio of M to In in each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than an atomic ratio of M to In in the second oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each include crystals in which c-axes are aligned.

5. The semiconductor device according to claim 1 , wherein each of the source electrode layer and the drain electrode layer contains one of Al, Cr, Cu, Ta, Ti, Mo, and W.

6. An electronic device comprising the semiconductor device according to claim 1 .

7. A method for manufacturing a semiconductor device comprising the steps of:
forming a stacked film of a first oxide semiconductor film and a second oxide semiconductor film over an insulating surface;
forming a conductive layer over the stacked film;
selectively etching the stacked film using the conductive layer as a mask; selectively etching the conductive layer to divide the conductive layer, thereby forming a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, a source electrode layer over the stack, and a drain electrode layer over the stack;
forming a third oxide semiconductor film over the insulating surface, the stack, the source electrode layer, and the drain electrode layer;
forming an oxide insulating film over the third oxide semiconductor film;
forming a gate electrode layer over the oxide insulating film;
selectively etching the oxide insulating film and the third oxide semiconductor film using the gate electrode layer as a mask to form a gate insulating film and a third oxide semiconductor layer;
forming an insulating layer over the source electrode layer, the drain electrode layer, and the gate electrode layer;
forming, in the insulating layer, a first opening where a first part of the second oxide semiconductor layer and a part of the source electrode layer are exposed, a second opening where a second part of the second oxide semiconductor layer and a part of the drain electrode layer are exposed, and a third opening where a part of the gate electrode layer is exposed; and
forming a first wiring electrically connected to the second oxide semiconductor layer and the source electrode layer in the first opening, a second wiring electrically connected to the second oxide semiconductor layer and the drain electrode layer in the second opening, and a third wiring electrically connected to the gate electrode layer in the third opening.

8. The method for manufacturing a semiconductor device according to claim 7 ,
wherein energy of a conduction band minimum of the first oxide semiconductor layer is closer to a vacuum level than energy of a conduction band minimum of the second oxide semiconductor layer by greater than or equal to 0.05 eV and less than or equal to 2 eV, and
wherein energy of a conduction band minimum of the third oxide semiconductor layer is closer to a vacuum level than the energy of the conduction band minimum of the second oxide semiconductor layer by greater than or equal to 0.05 eV and less than or equal to 2 eV.

9. The method for manufacturing a semiconductor device according to claim 7 ,
wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are each an In-M-Zn oxide,
wherein M is one of Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf,
wherein a material having a higher atomic ratio of M to In than an atomic ratio of M to In in the second oxide semiconductor layer is used for the first oxide semiconductor layer, and
wherein a material having a higher atomic ratio of M to In than the atomic ratio of M to In in the second oxide semiconductor layer is used for the third oxide semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 7 , wherein a material including crystals in which c-axes are aligned is used for each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer.

11. The method for manufacturing a semiconductor device according to claim 7 , wherein a layer containing one of Al, Cr, Cu, Ta, Ti, Mo, and W is used for each of the source electrode layer and the drain electrode layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Hanaoka Kazuya

Classifications

• H10D30/6743

  Silicon · CPC title

• H10D30/6737

  characterised by the electrode materials · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title