Transistors with an extension region having strips of differing conductivity type

Patent metadata

Field	Value
Publication number	US-9337333-B2
Application number	US-201414448198-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Dec 16, 2009
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

First claim

What is claimed is:

1. A transistor, comprising:
a gate dielectric over a semiconductor having a first conductivity type;
a control gate over the gate dielectric;
source and drain regions having a second conductivity type in the semiconductor having the first conductivity type; and
strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions;
wherein a portion of the semiconductor having the first conductivity type extends from one strip having the second conductivity type to an adjacent strip having the second conductivity type in a direction orthogonal to a direction extending from the source region to the drain region.

2. The transistor of claim 1 , further comprising a conductor strip over the gate dielectric and covering the portion of the semiconductor having the first conductivity type that extends between the adjacent strips having the second conductivity type.

3. The transistor of claim 2 , wherein the control gate and the conductor strip are polysilicon and wherein the first and second conductivity types are respectively p-type and n-type.

4. The transistor of claim 1 , wherein a width of the adjacent strips having the second conductivity type is substantially the same width as the portion of the semiconductor having the first conductivity type that extends between the adjacent strips having the second conductivity type.

5. The transistor of claim 1 , wherein the source/drain regions have a dose level of impurities of the second conductivity type that is about three orders of magnitude greater than a dose level of impurities of the second conductivity in the strips having the second conductivity type.

6. The transistor of claim 1 , wherein strips having the second conductivity type interposed between the control gate and at least one of the source and drain regions comprises strips having the second conductivity type between the control gate and both of the source and drain regions.

7. The transistor of claim 6 , wherein a number of strips having the second conductivity type within the semiconductor having the first conductivity type interposed between the control gate and the one of the source and drain regions is the same as a number of strips having the second conductivity type within the semiconductor having the first conductivity type interposed between the control gate and an other one of the source and drain regions.

8. The transistor of claim 1 , wherein the transistor is a Reduced Surface Field device and/or has a breakdown voltage of about 30 volts.

9. The transistor of claim 1 , wherein the transistor forms part of a memory device.

10. The transistor of claim 1 , further comprising a contact coupled to the source region and a contact coupled to the drain region.

11. The transistor of claim 10 , wherein a contact being coupled to the source region comprises a plurality of contacts coupled to a same source region and a contact being coupled to the drain region comprises a plurality of contacts coupled to a same drain region.

12. A transistor, comprising:
a gate dielectric over a semiconductor having a first conductivity type;
a control gate over the gate dielectric;
source and drain regions having a second conductivity type in the semiconductor having the first conductivity type;
strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions; and
a plurality of conductor strips over the gate dielectric, the conductor strips respectively covering portions of the semiconductor having the first conductivity type that are between the strips having the second conductivity type that are interposed between the control gate and the at least one of the first and second source/drain regions;
wherein the strips having the second conductivity type within the semiconductor that are interposed between the control gate and the at least one of the first and second source/drain regions and the portions of the semiconductor having the first conductivity type that are between the strips having the second conductivity type alternate.

13. The transistor of claim 12 , wherein a ratio of a width of each of the strips having the second conductivity type within the semiconductor to a width of each of the portions of the semiconductor having the first conductivity type is about 1:1.

14. A transistor, comprising:
a gate dielectric over a semiconductor having a first conductivity type;
a control gate over the gate dielectric;
a plurality of source regions having a second conductivity type in the semiconductor having the first conductivity type, wherein the source regions of the plurality of source regions are separated from each other by the semiconductor having the first conductivity type, and a plurality of drain regions having the second conductivity type in the semiconductor having the first conductivity type, wherein the drain regions of the plurality of drain regions are separated from each other by the semiconductor having the first conductivity type; and
a plurality of strips having the second conductivity type within the semiconductor having the first conductivity type, the strips having the second conductivity type within the semiconductor interposed between the control gate and respective ones of the plurality of separated source regions and/or between the control gate and respective ones of the plurality of separated drain regions.

15. The transistor of claim 14 , wherein the plurality of source regions are at ends of the strips having the second conductivity type within the semiconductor interposed between the control gate and the respective ones of the plurality of source regions and the plurality of drain regions are at ends of the strips having the second conductivity type within the semiconductor interposed between the control gate and the respective ones of the plurality of drain regions.

16. The transistor of claim 14 , further comprising a contact coupled to each of the plurality of source regions and to each of the plurality of drain regions.

17. The transistor of claim 14 , wherein the strips having the second conductivity type within the semiconductor and portions of the semiconductor having the first conductivity type alternate.

18. The transistor of claim 14 , further comprising a plurality of conductor strips over the gate dielectric, the conductor strips respectively covering portions of the semiconductor having the first conductivity type that are between the strips having the second conductivity type within the semiconductor.

19. The transistor of claim 18 , wherein the strips having the second conductivity type within the semiconductor and the portions of the semiconductor having the first conductivity type that are between the strips having the second conductivity type within the semiconductor alternate.

20. The transistor of claim 14 , wherein a number of the strips having the second conductivity type within the semiconductor interposed between the control gate and the respective ones of the plurality of source regions is the same as a number of the strips having the second conductivity type within the semiconductor interposed between the control gate and the respective ones of the plurality of drain regions.

Assignees

• Micron Technology Inc

Inventors

• Smith Michael
• Mikhalev Vladimir
• Sharma Puneet
• Shafi Zia Alan
• Fulford Henry Jim

Classifications

• H10P30/22

  using masks · CPC title

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D64/27

  Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title