Shallow trench isolation in bulk substrate

Patent metadata

Field	Value
Publication number	US-9337260-B2
Application number	US-201414549559-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Jan 8, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a plurality of first insulators in a bulk substrate;
a common insulating layer surrounding the sidewall and the bottom of said first insulators in said bulk substrate; and
projected portions of said bulk substrate being directly and totally on top surface of said common insulating layer.

2. The semiconductor structure according to claim 1 , wherein said projected portions of said bulk substrate are between each of said first insulators on said common insulating layer.

3. The semiconductor structure according to claim 1 , further comprising a second insulator on each of said first insulators and a buffer layer on the sidewall and the bottom of each said second insulator, wherein a part of said buffer layer interfaces between said first insulator and said second insulator.

4. The semiconductor structure according to claim 3 , wherein the outer sidewall of said buffer layer and the sidewall of said first insulator are leveled.

5. The semiconductor structure according to claim 3 , wherein the material of said first insulator and said second insulator is silicon oxide.

6. The semiconductor structure according to claim 3 , wherein the material of said buffer layer comprises stress buffer film, silicon nitride, or silicon carbonitride.

7. The semiconductor structure according to claim 1 , wherein said projected portions of said bulk substrate are fin structures for fin field effect transistors.

8. The semiconductor structure according to claim 7 , wherein said first insulators and said common insulating layer serve as isolating structures between said fin structures.

9. The semiconductor structure according to claim 7 , further comprising a High-k material layer on said fin structures.

10. The semiconductor structure according to claim 7 , further comprising a gate structure on each of said fin structures traversing said fin structures.

Assignees

• United Microelectronics Corp

Inventors

• Liou En-Chiuan
• Tsao Po-Chao
• Liang Chia-Jui
• Wu Jia-Rong

Classifications

• H10W10/0147

  the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title