Backplane of flat panel display and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9337211-B2
Application number	US-201314092477-A
Country	US
Kind code	B2
Filing date	Nov 27, 2013
Priority date	Jun 20, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Provided are a backplane for a flat panel display device and a method of manufacturing the backplane. The method of manufacturing the backplane for a flat panel display device includes forming an insulation substrate on a glass substrate, forming a protection layer on the insulation substrate, the protection layer including a first opening exposing a portion of the insulation substrate, forming a first hole in the insulation substrate by removing the portion of the insulation substrate exposed by the first opening, and forming a transistor on the protection layer, the transistor including an active layer, a gate electrode, a source electrode, and a drain electrode. The insulation substrate may include a transistor area including the transistor, and a non-transistor area excluding the transistor and including the first hole.

First claim

What is claimed is:

1. A method of manufacturing a backplane for a flat panel display device, the method comprising:
forming a protection layer on an insulation substrate, the protection layer comprising a first opening exposing a portion of the insulation substrate;
forming a first hole in the insulation substrate by removing the portion of the insulation substrate exposed by the first opening, wherein a widest width of the first hole is greater than a width of the first opening; and
forming a transistor on the protection layer, the transistor comprising an active layer, a gate electrode, a source electrode, and a drain electrode,
forming a first insulating layer covering the transistor, wherein the first insulating layer fills at least a portion of the first hole,
wherein the insulation substrate comprises a transistor area comprising the transistor, and a non-transistor area in which the first hole is formed and in which the transistor is omitted.

2. The method of claim 1 , wherein a width of the first hole is wider than a width of the first opening.

3. The method of claim 1 , wherein forming the first hole comprises removing the portion of the insulation substrate exposed by the first opening such that a distance from a center of the first opening to a sidewall of the first hole is greater than a distance from the center of the first opening to a side end of the first opening.

4. The method of claim 1 , wherein the protection layer protrudes in an overhang structure with respect to the first hole at the first opening.

5. The method of claim 1 , wherein forming the transistor further comprises depositing at least some materials comprising the transistor into the first hole, forming a dummy pattern.

6. The method of claim 5 , wherein a height of the dummy pattern is shorter than a height of the insulation substrate.

7. The method of claim 5 , wherein the first insulating layer comprises a second hole exposing a portion of the source electrode or drain electrode.

8. The method of claim 7 , further comprising forming a pixel electrode on the first insulating layer, the pixel electrode being electrically connected to either of the source electrode or the drain electrode via the second hole.

9. The method of claim 8 , further comprising forming a second insulating layer on the first insulating layer covering an edge of the pixel electrode, the second insulating layer comprising a second opening exposing at least a portion of the pixel electrode.

10. The method of claim 9 , further comprising:
forming an intermediate layer comprising an organic emissive layer on the at least a portion of the pixel electrode exposed by the second opening; and
forming an opposite electrode on the pixel electrode with the intermediate layer therebetween.

11. The method of claim 1 , wherein forming the first hole comprises removing the portion of the insulation substrate exposed by the first opening using an ashing process.

12. The method of claim 1 , wherein the active layer comprises amorphous silicon or polysilicon, and forming the transistor further comprises using a low-temperature polycrystalline silicon (LTPS) process.

13. A backplane for a flat panel display device, the backplane comprising:
an insulation substrate comprising a transistor area comprising a transistor, and a non-transistor area including a first hole;
a protection layer positioned on the insulation substrate, the protection layer comprising a first opening corresponding to the first hole;
a transistor positioned on the protection layer, the transistor comprising an active layer, a gate electrode, a source electrode, and a drain electrode; and
a first insulating layer covering the transistor, the first insulating layer comprising a second hole exposing a portion of the source electrode or drain electrode,
wherein the first insulating layer fills at least a portion of the first hole,
wherein a widest width of the first hole is greater than a width of the first opening.

14. The backplane of claim 13 , a width of the first hole is greater than the width of the first opening, and the protection layer protrudes in an overhang structure with respect to the first hole at the first opening.

15. The backplane of claim 13 , further comprising a pixel electrode positioned on the first insulating layer, the pixel electrode electrically connected to either the source electrode or the drain electrode via the second hole.

16. The backplane of claim 15 , further comprising a second insulating layer positioned on the first insulating layer covering an edge of the pixel electrode, the second insulating layer comprising a second opening exposing at least a portion of the pixel electrode.

17. The backplane of claim 16 , further comprising:
an intermediate layer positioned on the at least a portion of the pixel electrode exposed by the second opening, the intermediate layer comprising an organic emissive layer; and
an opposite electrode positioned opposite the pixel electrode, with the intermediate layer therebetween.

18. The backplane of claim 13 , wherein the active layer comprises amorphous silicon or polysilicon.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Jong-Yun
• Yu Cheol-Ho

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/88

  Dummy elements, i.e. elements having non-functional features · CPC title

• H10D86/411 Primary

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title

• H10D86/021

  of multiple TFTs · CPC title