Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9337199-B2
Application number	US-201314089356-A
Country	US
Kind code	B2
Filing date	Nov 25, 2013
Priority date	May 2, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a first region and a second region on a surface thereof;
a first semiconductor fin on the first region of the substrate wherein the first semiconductor fin includes a first trench therethrough;
a first gate electrode in the first trench;
first and second source/drain regions in the first semiconductor fin wherein the first gate electrode is between the first and second source/drain regions;
a second semiconductor fin on the second region of the substrate wherein the second semiconductor fin includes a second trench therethrough;
a second gate electrode in the second trench; and
third and fourth source/drain regions in the second semiconductor fin wherein the second gate electrode is between the third and fourth source/drain regions,
wherein the first region comprises a memory cell array region and the second region comprises a peripheral circuit region.

2. The semiconductor device of claim 1 wherein a depth of the second trench into the second semiconductor fin is less than a greatest height of the second semiconductor fin above the surface of the substrate, and wherein portions of the second gate electrode extend onto portions of sidewalls of the second semiconductor fin between the second trench and the surface of the substrate.

3. The semiconductor device of claim 2 further comprising:
an isolation layer on the second region of the substrate adjacent to the second semiconductor fin, wherein the second trench extends through the second semiconductor fin and through the isolation layer on opposite sides of the second semiconductor fin, and wherein a depth of the second trench in the isolation layer is greater than a depth of the second trench in the second semiconductor fin.

4. The semiconductor device of claim 2 wherein a depth of the first trench into the first semiconductor fin is less than a greatest height of the first semiconductor fin above the surface of the substrate, and wherein portions of the first gate electrode extend onto portions of sidewalls of the first semiconductor fin between the first trench and the surface of the substrate.

5. The semiconductor device of claim 4 further comprising:
an isolation layer on the first region of the substrate adjacent to the first semiconductor fin, wherein the first trench extends through the first semiconductor fin and through the isolation layer on opposite sides of the first semiconductor fin, and wherein a depth of the first trench in the isolation layer is greater than a depth of the first trench in the first semiconductor fin.

6. The semiconductor device of claim 1 wherein a width of the first trench is less than a width of the second trench, and/or wherein a width of the first gate electrode is less than a width of the second gate electrode.

7. The semiconductor device of claim 1 wherein a depth of the first trench in the first semiconductor fin is different than a depth of the second trench in the second semiconductor fin.

8. The semiconductor device of claim 7 wherein a depth of the first trench in the first semiconductor fin is greater than a depth of the second trench in the second semiconductor fin.

9. The semiconductor device of claim 1 wherein the second gate electrode is recessed in the second trench.

10. The semiconductor device of claim 1 wherein each of the first gate electrode and the second gate electrode comprises at least one metal containing layer.

11. The semiconductor device of claim 1 wherein the first gate electrode is recessed a first distance in the first trench, wherein the second gate electrode is recessed a second distance in the second trench, and wherein the first and second distances are different.

12. The semiconductor device of claim 1 wherein the first gate electrode comprises a material not included in the second gate electrode, and/or wherein the second gate electrode includes a material not included in the first gate electrode.

13. The semiconductor device of claim 1 further comprising:
a third semiconductor fin on the second region of the substrate wherein the third semiconductor fin includes a third trench therethrough;
a third gate electrode in the third trench; and
fifth and sixth source/drain regions in the third semiconductor fin wherein the third gate electrode is between the fifth and sixth source/drain regions.

14. The semiconductor device of claim 13 wherein a depth of the third trench into the third semiconductor fin is greater than a depth of the second trench into the second semiconductor fin.

15. The semiconductor device of claim 13 wherein a first peripheral circuit transistor is defined by the second gate electrode and the third and fourth source/drain regions, wherein the first peripheral circuit transistor has a first threshold voltage, wherein a second peripheral circuit transistor is defined by the third gate electrode and the fifth and sixth source/drain regions, wherein the second peripheral circuit transistor has a second threshold voltage, and wherein the first and second threshold voltages are different.

16. The semiconductor device of claim 13 wherein the second and third gate electrodes have different work functions.

17. The semiconductor device of claim 13 wherein the second gate electrode comprises a layer including lanthanum oxide, and wherein the third gate electrode comprises a layer including aluminum oxide.

18. The semiconductor device of claim 13 wherein the third and fourth source/drain regions comprise n-type source/drain regions, and wherein the fifth and sixth source/drain regions comprise p-type source/drain regions.

19. The semiconductor device of claim 18 wherein the third gate electrode has a work function that is higher than a work function of the second gate electrode.

20. The semiconductor device of claim 1 wherein the first semiconductor fin is aligned in a first direction, wherein the second semiconductor fin is aligned in a second direction, and wherein the first and second directions are non-parallel.

21. The semiconductor device of claim 1 wherein the first gate electrode comprises a word line, the semiconductor device further comprising:
a memory cell capacitor including a memory cell storage node electrically coupled to the first source/drain region; and
a bit line electrically coupled to the second source/drain region.

22. The semiconductor device of claim 1 wherein the first gate electrode and the first and second source/drain regions define a memory cell transistor, and wherein the second gate electrode and the third and fourth source/drain regions define a peripheral circuit transistor.

23. The semiconductor device of claim 1 wherein depths of the first and second source/drain regions into the first semiconductor fin are greater than a depth of the first trench into the first semiconductor fin.

24. A semiconductor memory device comprising:
a substrate including a first region and a second region on a surface thereof;
a first semiconductor fin on the first region of the substrate wherein the first semiconductor fin includes a first trench therethrough;
a first gate electrode in the first trench;
first and second source/drain regions in the first semiconductor fin wherein the first gate electrode is between the first and second source/drain regions, and wherein the first gate electrode and the first and second source/drain regions define a memory cell transistor;
a second

Assignees

• Kim Jiyoung
• Jang Sungho
• Kim Kang-Uk
• Kim Kyung-Eun
• Kim Daeik
• Kim Hyoungsub
• Son Nakjin
• Lee Dong Jin
• Hwang Yoosang
• Hwang Jihye
• Samsung Electronics Co Ltd

Inventors

• Kim Jiyoung
• Jang Sungho
• Kim Kang-Uk
• Kim Kyung-Eun
• Kim Daeik
• Kim Hyoungsub
• Son Nakjin
• Lee Dong Jin
• Hwang Yoosang
• Hwang Jihye

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L27/10826 Primary

  Electricity · mapped topic