Semiconductor device and a method of manufacturing the same and designing the same

Patent metadata

Field	Value
Publication number	US-9337147-B2
Application number	US-201514745040-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Nov 20, 2000
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.

First claim

What is claimed is:

1. A semiconductor device comprising:
grooves formed in a semiconductor substrate such that the grooves define an active region and a plurality of first dummy regions;
element isolation insulating films filled in the grooves;
a MISFET formed in the active region;
a first interlayer insulation film formed over the MISFET, the active region and the first dummy regions;
a first wiring, a plurality of first dummy wirings and a plurality of second dummy wirings formed over the first interlayer insulation film, respectively; and
a second interlayer insulation film formed over the first wiring, the first dummy wirings and the second dummy wirings,
wherein the first dummy regions do not include the MISFET,
wherein the first wiring is electrically connected with the MISFET,
wherein the first dummy wirings and the second dummy wirings are not electrically connected with the MISFET,
wherein each of the first dummy regions is arranged with a same pitch,
wherein a planar size of each of the first dummy wirings is larger than a planar size of each of the second dummy wirings,
wherein each of the first dummy wirings is arranged with a same pitch,
wherein each of the second dummy wirings is arranged with a same pitch,
wherein the second dummy wirings are arranged next to the first wiring, and between the first wiring and the first dummy wirings,
wherein the pitch of the first dummy wirings is larger than the pitch of the second dummy wirings,
wherein, in planar view, the first and second dummy wirings are arranged over the first dummy regions, and
wherein the first wiring, the first dummy wirings and the second dummy wirings are comprised of copper as a major component.

2. The semiconductor device according to claim 1 ,
wherein a gate electrode of the MISFET includes a first silicon film and a second silicon film formed over the first silicon film, and
wherein each of the grooves is formed by using the first silicon film as a mask.

Assignees

• Renesas Electronics Corp

Inventors

• Kuroda Kenichi
• Watanabe Kozo
• Yamamoto Hirohiko

Classifications

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W15/01

  Manufacture or treatment · CPC title