Chip package and method for forming the same

Patent metadata

Field	Value
Publication number	US-9337115-B2
Application number	US-201514676671-A
Country	US
Kind code	B2
Filing date	Apr 1, 2015
Priority date	Apr 2, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a sensing device and a conducting pad therein. The sensing device and the conducting pad are adjacent to the first surface. The conducting pad has a sidewall laterally protruding from a sidewall of the substrate. An encapsulation layer is attached to the first surface of the substrate to cover the sensing device and the conducting pad. A redistribution layer is disposed on the second surface of the substrate and extends to contact the sidewall of the conducting pad. An end of the redistribution layer protrudes from the first surface of the substrate and is level with a third surface of the encapsulation layer that is opposite to the first surface. A method of forming the chip package is also provided.

First claim

What is claimed is:

1. A chip package, comprising:
a substrate having a first surface and a second surface opposite thereto, wherein the substrate comprises a sensing device and at least one conducting pad therein, and the sensing device and the at least one conducting pad are adjacent to the first surface, and wherein the at least one conducting pad has a sidewall laterally protruding from a sidewall of the substrate;
an encapsulation layer attached to the first surface of the substrate to cover the sensing device and the at least one conducting pad; and
a redistribution layer disposed on the second surface of the substrate and extending to contact the sidewall of the at least one conducting pad, wherein an end of the redistribution layer protrudes from the first surface of the substrate and is aligned with a third surface of the encapsulation layer that is opposite to the first surface of the substrate.

2. The chip package as claimed in claim 1 , wherein a sidewall of the encapsulation layer is aligned with the sidewall of the at least one conducting pad.

3. The chip package as claimed in claim 1 , further comprising a protection layer covering the encapsulation layer and the end of the redistribution layer.

4. The chip package as claimed in claim 3 , wherein a hardness of the protection layer is greater than that of the encapsulation layer.

5. The chip package as claimed in claim 1 , further comprising an insulating layer disposed between the second surface of the substrate and the redistribution layer.

6. The chip package as claimed in claim 5 , wherein the insulating layer covers the sidewall of the substrate.

7. The chip package as claimed in claim 1 , further comprising a passivation layer disposed on the redistribution layer.

8. The chip package as claimed in claim 7 , wherein a surface of the passivation layer is aligned with the third surface of the encapsulation layer.

9. The chip package as claimed in claim 7 , wherein the passivation has an opening exposing a portion of the redistribution layer on the second surface of the substrate.

10. The chip package as claimed in claim 9 , further comprising a conducting structure disposed on the exposed portion of the redistribution layer.

11. The chip package as claimed in claim 1 , further comprising a support substrate disposed between the second surface of the substrate and the redistribution layer.

12. The chip package as claimed in claim 11 , further comprising an adhesive layer disposed between the second surface of the substrate and the support substrate, wherein the adhesive layer extends between the sidewall of the substrate and the redistribution layer.

13. A method for forming a chip package, comprising:
providing a substrate having a first surface and a second surface opposite thereto, wherein the substrate comprises a sensing device and at least one conducting pad therein, and the sensing device and the at least one conducting pad are adjacent to the first surface, and wherein the at least one conducting pad has a sidewall laterally protruding from a sidewall of the substrate;
attaching an encapsulation layer to the first surface of the substrate to cover the sensing device and the at least one conducting pad; and
forming a redistribution layer on the second surface of the substrate, wherein the redistribution layer extends to contact the sidewall of the at least one conducting pad, and wherein an end of the redistribution layer protrudes from the first surface of the substrate and is aligned with a third surface of the encapsulation layer that is opposite to the first surface of the substrate.

14. The method as claimed in claim 13 , wherein a sidewall of the encapsulation layer is aligned with the sidewall of the at least one conducting pad.

15. The method as claimed in claim 13 , further comprising forming a protection layer to cover the encapsulation layer and the end of the redistribution layer.

16. The method as claimed in claim 15 , wherein a hardness of the protection layer is greater than that of the encapsulation layer.

17. The method as claimed in claim 13 , further comprising forming an insulating layer between the second surface of the substrate and the redistribution layer.

18. The method as claimed in claim 17 , wherein the insulating layer covers the sidewall of the substrate.

19. The method as claimed in claim 13 , further comprising forming a passivation layer on the redistribution layer.

20. The method as claimed in claim 19 , wherein a surface of the passivation layer is aligned with the third surface of the encapsulation layer.

21. The method as claimed in claim 19 , further comprising forming an opening in the passivation to expose a portion of the redistribution layer on the second surface of the substrate.

22. The method as claimed in claim 21 , further comprising forming a conducting structure on the exposed portion of the redistribution layer.

23. The method as claimed in claim 13 , further comprising providing a support substrate between the second surface of the substrate and the redistribution layer.

24. The method as claimed in claim 23 , wherein the support substrate is attached to the second surface of the substrate by an adhesive layer, and wherein the adhesive layer extends between the sidewall of the substrate and the redistribution layer.

Assignees

• Xintec Inc

Inventors

• Liu Chien-Hung

Classifications

• H10P14/6328

  Deposition from the gas or vapour phase · CPC title

• H10P14/687

  the materials being fluorocarbon compounds, e.g. (CHxFy) n or polytetrafluoroethylene · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title