Air gap formation between bit lines with side protection

Patent metadata

Field	Value
Publication number	US-9337085-B2
Application number	US-201414340953-A
Country	US
Kind code	B2
Filing date	Jul 25, 2014
Priority date	Feb 12, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.

First claim

It is claimed:

1. A method of forming bit lines of a nonvolatile memory comprising:
forming a sacrificial layer of a sacrificial material on a dielectric layer with metal vias above a memory array;
subsequently forming a plurality of elongated openings in the sacrificial layer, the plurality of elongated openings aligned with upper surfaces of the metal vias;
subsequently performing selective oxidation of exposed sacrificial material of the sacrificial layer in the plurality of elongated openings to form first oxide portions along sides of the elongated openings, and of exposed sacrificial material of the sacrificial layer between the plurality of elongated openings to form second oxide portions, without significantly oxidizing exposed upper surfaces of the metal vias or exposed surfaces of the dielectric layer;
subsequently depositing a barrier layer over the first and second oxidized portions;
subsequently depositing a bit line metal over the barrier layer;
subsequently removing excess bit line metal and the second oxide portions to form individual bit lines and to expose portions of sacrificial material between bit lines; and
subsequently removing the portions of sacrificial material to form air gaps between bit lines.

2. The method of claim 1 wherein the sacrificial material comprises amorphous silicon and the oxide portions comprise silicon dioxide.

3. The method of claim 1 wherein the sacrificial layer is formed on an etch stop layer and wherein the plurality of elongated openings in the sacrificial layer are formed by etching through the sacrificial layer and stopping on the etch stop layer.

4. The method of claim 1 wherein the bit line metal is copper or tungsten and the barrier layer comprises at least one of: titanium, titanium nitride, titanium oxide, tantalum, or tantalum oxide.

5. The method of claim 1 wherein the oxidation of the exposed sacrificial material provides an oxide thickness in the range of about 2 nanometers to 5 nanometers of oxide along sides of the plurality of openings in the sacrificial material.

6. The method of claim 1 wherein the sacrificial material is removed using a selective etch that has a higher etch rate for the sacrificial material than for the oxide portions so that substantially all sacrificial material is removed while the oxide portions remain substantially intact.

7. The method of claim 1 further comprising: prior to removing the portions of sacrificial material, selectively forming portions of protective material on upper surfaces of the bit lines without forming the protective material on the portions of sacrificial material.

8. The method of claim 7 wherein selectively forming the portions of protective material on the upper surfaces of the bit lines includes selective Chemical Vapor Deposition (CVD) of a nucleation layer and subsequent deposition of an additional layer by electroless plating on the nucleation layer.

9. The method of claim 8 wherein the nucleation layer and the additional layer are formed of tungsten.

Assignees

• Sandisk Technologies Inc

Inventors

• Sel Jong Sun
• Gunji-Yoneoka Marika
• Takeguchi Naoki
• Park Chan
• Pham Tuan D
• Tokunaga Kazuya

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title