Sense amp activation according to word line common point

Patent metadata

Field	Value
Publication number	US-9336862-B2
Application number	US-201414288486-A
Country	US
Kind code	B2
Filing date	May 28, 2014
Priority date	May 28, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Systems, methods, and other embodiments associated with controlling when a sense amplifier is activated are described. In one embodiment, a device includes detection logic connected to a plurality of word lines in a memory and configured to generate a signal upon detecting one of the plurality of word lines being activated. The device includes a sense amplifier configured to read a value from a bit line associated with an activated word line of the plurality of word lines upon receiving the signal.

First claim

What is claimed is:

1. A device, comprising:
detection logic connected to a plurality of word lines in a memory and configured to generate a signal upon detecting one of the plurality of word lines being activated; and
a sense amplifier configured to read a value from a bit line associated with an activated word line of the plurality of word lines upon receiving the signal from the detection logic,
wherein the detection logic is configured to generate the signal from a common connection point with the plurality of word lines that reduces a margin of time between the bit line being activated and the sense amplifier being enabled.

2. The device of claim 1 , wherein the bit line is activated when a memory cell associated with the bit line is activated by the activated word line, and wherein the common connection point includes at least one logic gate connected to one of the plurality of word lines.

3. The device of claim 1 , wherein the common connection point is located on the plurality of word lines after a plurality of logic gates connected in series along the plurality of word lines and prior to a plurality of memory cells in the memory, wherein the detection logic is configured to use the common connection point to determine when one of the plurality of word lines transitions to an active state, and to generate the signal when one of the plurality of word lines transitions to the active state.

4. The device of claim 1 , wherein the detection logic is configured to generate the signal by detecting a transition of one of the plurality of word lines from an inactive state to an active state.

5. The device of claim 1 , further comprising:
control logic configured to receive a memory request and to activate one of the plurality of word lines associated with an address in the memory request, wherein the plurality of word lines correlate with rows of memory cells.

6. The device of claim 1 , wherein the detection logic is configured to generate the signal by detecting a transition of one of the plurality of word lines at the common connection point along the plurality of word lines, wherein the common connection point is a connection on the plurality of word lines that routes a signal to the sense amplifier and to a memory cell that provides a value on the bit line.

7. The device of claim 1 , wherein the device is a static random-access memory (SRAM).

8. A method, comprising:
activating, in a memory, a word line associated with an address from a memory request; and
providing, from a common connection point on the word line, an activation signal to (i) a memory cell and (ii) a sense amplifier based, at least in part, on the common connection point transitioning from an inactive state to an active state, wherein providing the activation signal to the memory cell activates a bit line associated with the memory cell, wherein providing the activation signal from the common connection point reduces a margin of time between activating the bit line and activating sense amplifier.

9. The method of claim 8 , wherein providing the activation signal from the common connection point simultaneously provides the activation signal to the sense amplifier and the memory cell.

10. The method of claim 8 , further comprising:
receiving, prior to activating the word line, a request to access the memory that includes an address of the memory cell; and
reading, by the sense amplifier, a value from the bit line that is stored in the memory cell upon the sense amplifier being activated in response to the activation signal from the common connection point.

11. The method of claim 8 , wherein providing the activation signal to the memory cell includes activating the word line that is associated with a row of memory cells that includes the memory cell.

12. The method of claim 8 , wherein providing the signal occurs upon the word line transitioning from an inactive state to an active state at the common connection point.

13. The method of claim 8 , wherein providing the activation signal to the sense amplifiers activates the sense amplifier causing the sense amplifier to read a value from the bit line.

14. A memory, comprising:
a plurality of word lines connected to a controller and connected to a plurality of memory cells;
a detection logic connected to the plurality of word lines and configured to generate an activation signal upon detecting one of the plurality of word lines transitioning from an inactive state to an active state; and
a sense amplifier connected to the detection logic and connected to the plurality of memory cells via a bit line, wherein a common connection point is a circuit connection from which the activation signal is provided to the sense amplifier to reduce a margin of time between activating the sense amplifier and the bit line.

15. The memory of claim 14 , wherein the plurality of word lines include a plurality of logic gates connected in series, and wherein the detection logic is connected to the plurality of word lines at a location that is after the plurality of logic gates and prior to the plurality of memory cells.

16. The memory of claim 14 , wherein the detection logic is configured to provide the activation signal to the sense amplifier to activate the sense amplifier, and wherein the sense amplifier is configured to read a value from the bit line in response to receiving the activation signal.

17. The memory of claim 14 , wherein the detection logic is connected to the plurality of word lines at the common connection point that is a location that is after one or more logic gates.

18. The memory of claim 14 , wherein the plurality of memory cells include rows of memory cells that are each connected to one of the plurality of word lines.

19. The memory of claim 14 , wherein the controller is configured with inputs to receive a clock signal, a memory address and a read enable signal, and wherein the memory is a static random access memory (SRAM).

Assignees

• Oracle Int Corp

Inventors

• Won Myung Gyoo
• Park Heechoul
• Nguyen Thu Hanh

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title