Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits

Patent metadata

Field	Value
Publication number	US-9336345-B2
Application number	US-201314040037-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

First claim

What is claimed is:

1. A method for converting a planar integrated circuit design to a non-planar integrated circuit design comprising:
identifying, using a computer processor of a computing system, a rectangular silicon active area in the planar integrated circuit design;
superimposing, using the computer processor, a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines;
generating, using the computer processor, a rectangular active silicon marker area encompassing the silicon active area;
generating, using the computer processor, fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area; and
removing, using the computer processor, a portion of the fin mandrels from the design grid so as to generate the non-planar integrated circuit design, wherein removing the portion of the fin mandrels from the design grid comprises removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

2. The method of claim 1 , wherein identifying the rectangular silicon active area comprises identifying a plurality of rectangular silicon active areas.

3. The method of claim 2 , wherein generating the rectangular active silicon marker area comprises generating the rectangular active silicon marker area encompassing each rectangular silicon active area of the plurality of rectangular silicon active areas.

4. The method of claim 3 , wherein generating the rectangular active silicon marker area comprises generating a plurality of rectangular active silicon marker areas, each rectangular active silicon marker area of the plurality of rectangular active silicon marker areas encompassing at least two rectangular silicon active areas of the plurality of rectangular silicon active areas.

5. The method of claim 4 , wherein an area defined by an active silicon marker area of the plurality of active silicon marker areas is greater than an area defined by a combination of areas of each silicon active area of the plurality of silicon active areas within the active silicon marker.

6. The method of claim 1 , wherein generating the rectangular active silicon marker area comprises generating the rectangular active silicon marker area such that two sides thereof are coincident with two respective grid lines of the plurality of grid lines.

7. The method of claim 6 , wherein superimposing the FinFET design grid comprises superimposing the FinFET design grid such that at least one of the two sides of the rectangular silicon active area that are parallel to the grid lines is not coincident with any grid line of the plurality of grid lines.

8. The method of claim 7 , further comprising re-sizing the rectangular silicon active area by inwardly moving the at least one of the two side of the rectangular silicon active area so as to coincide with a nearest inward grid line of the plurality of grid lines.

9. The method of claim 6 , wherein superimposing the FinFET design grid comprises superimposing the FinFET design grid such that both of the two side of the rectangular silicon active area that are parallel to the grid lines are not coincident with any of grid line of the plurality of grid lines.

10. The method of claim 9 , further comprising re-sizing the rectangular silicon active area by inwardly moving both of the two sides of the rectangular silicon active area so as to coincide with respective nearest inward grid lines of the plurality of grid lines.

11. The method of claim 1 , wherein generating fin mandrels comprises generating fin mandrels that are longitudinally-centered on respective grid lines of the plurality of grid lines.

12. The method of claim 1 , wherein identifying the rectangular silicon active area comprises identifying the rectangular silicon active area of a single macro cell.

13. The method of claim 12 , wherein superimposing the FinFET design grid comprises superimposing the FinFET design grid oriented on an origin of the single macro cell.

14. The method of claim 13 , wherein superimposing the FinFET design grid comprises superimposing the FinFET design grid so as to overlie only the single macro cell.

15. The method of claim 14 , wherein generating the non-planar design comprises generating a non-planar design for the single macro cell, and further comprising merging the non-planar design with a further non-planar design to generate a reticle-level non-planar design.

16. A method for fabricating an integrated circuit comprising:
identifying a rectangular silicon active area in the planar integrated circuit design;
superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines;
generating a rectangular active silicon marker area encompassing the silicon active area;
generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area; and
removing a portion of the fin mandrels from the design grid so as to generate the non-planar integrated circuit design, wherein removing the portion of the fin mandrels from the design grid comprises removing the fin mandrels from areas of the design grid outside of the active silicon marker area;
generating a photolithographic mask based on the non-planar integrated circuit design; and
forming a non-planar integrated circuit in a semiconductor substrate by exposing a light source through the photolithographic mask and onto the semiconductor substrate.

17. The method of claim 16 , further comprising depositing a photoresist material onto the semiconductor substrate prior to exposing the semiconductor substrate to the light source.

18. The method of claim 16 , wherein generating a photolithographic mask comprises generating a plurality of photolithographic masks comprising a photolithographic mask set, and further comprising exposing the semiconductor substrate to the light source through each photolithographic mask of the photolithographic mask set.

19. A computer program product, comprising:
a first set of instructions, stored in at least one non-transitory machine-readable medium, executable by at least one processing unit to identify a rectangular silicon active area in the planar integrated circuit design;
a second set of instructions, stored in the at least one non-transitory machine-readable medium, executable by the at least one processing unit to superimpose a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines;
a third set of instructions, stored in the at least one non-transitory machine-readable medium, executable by the at least one processing unit to generate a rectangular active silicon marker area encompassing the silicon active area;
a fourth set of instructions, stored in the at least one non-transitory machine-readable medium, executable by the at least one processing unit to generate fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area; and
a fifth set of instructions, stored in

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Tan Soon Yoeng
• Ramamoorthy Srinidhi
• Ho Chye Ee Angeline
• Knorr Andreas
• Johnson Frank Scott

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title