Accelerating cache state transfer on a directory-based multicore architecture

Patent metadata

Field	Value
Publication number	US-9336146-B2
Application number	US-201013319159-A
Country	US
Kind code	B2
Filing date	Dec 29, 2010
Priority date	Dec 29, 2010
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.

First claim

What is claimed is:

1. A non-transitory computer-readable storage media having instruction stored thereon to accelerate a cache state transfer in a multicore processor, the instructions being executable by the multicore processor to perform or cause to be performed operations comprising:
initiating migration of a thread executing on a first core at a first tile in the multicore processor from the first tile to a second tile in the multicore processor, the first tile comprising the first core, a first directory that maps a first set of block addresses and a first cache, the second tile comprising a second core, a second directory that maps a second set of block addresses and a second cache, wherein the first directory and the second directory are components of a main memory coupled to the multicore processor, the main memory including a shared memory architecture, and the main memory is configured to operate with a directory based coherence protocol;
determining block addresses of blocks to be transferred from the first cache to the second cache based on the migration of the thread executing on the first core at the first tile to the second tile in the multicore processor, wherein the block addresses of the blocks are determined by scanning a cache tag array of the first cache;
identifying a third tile in the multicore processor, the third tile comprising a third directory that maps a third set of block addresses, the third set of block addresses corresponding to the block addresses of the blocks to be transferred from the first cache to the second cache, wherein the third directory indicates that the first cache contains the blocks and the second cache does not share the blocks, and the third directory is a component of the main memory coupled to the multicore processor;
updating the third directory to reflect that the second cache shares the blocks by sending a message from the first tile to the third tile including a list of the block addresses of the blocks to be transferred from the first cache to the second cache, and an identifier of the second cache to which the blocks are to be transferred;
in response to receiving a successful directory update acknowledgement from the third tile at the first tile, transferring the blocks from the first cache in the first tile to the second cache in the second tile to complete the migration of the thread from the first tile to the second tile;
identifying a cache invalidation and a cache intervention request for at least one of the blocks of the first cache at the first tile, wherein the first tile further includes a transfer status table;
determining whether a first type of transfer operation has been completed, wherein the first type of transfer operation is determined to be completed when the transfer status table indicates that the blocks of the first cache have been transferred from the first cache to the second cache and also when the third directory has not been updated to reflect that the second cache shares the blocks of the first cache; and
in response to determining that the first type of transfer operation has been completed, forwarding one of the cache invalidation and the cache intervention request from the first tile to the second tile.

2. The non-transitory computer-readable storage media of claim 1 , wherein updating the third directory to reflect that the second cache shares the blocks comprises, in response to receiving the message at the third tile, updating the third directory to reflect that the second cache shares the block addresses of the blocks as contained in the list of the block addresses of the blocks.

3. The non-transitory computer-readable storage media of claim 1 , wherein updating the third directory to reflect that the second cache shares the blocks comprises updating a bit vector to reflect that the second cache contains the blocks, wherein the third directory comprises the bit vector that includes bits, where each of the bits is associated with a corresponding tile in the multicore processor, a value of each of the bits specifying whether the corresponding tile includes a corresponding cache that contains the blocks.

4. The non-transitory computer-readable storage media of claim 1 , wherein transferring the blocks from the first cache to the second cache comprises transferring the blocks from the first cache to the second cache before the third directory is updated to reflect that the second cache shares the blocks.

5. The non-transitory computer-readable storage media of claim 1 , wherein transferring the blocks from the first cache to the second cache comprises transferring the blocks from the first cache to the second cache concurrently with updating the third directory to reflect that the second cache shares the blocks.

6. The non-transitory computer-readable storage media of claim 1 , wherein transferring the blocks from the first cache to the second cache comprises replicating the blocks between the first cache and the second cache.

7. The non-transitory computer-readable storage media of claim 6 , wherein replicating the blocks between the first cache and the second cache comprises sending an instruction to update the main memory coupled to the multicore processor to clean dirty entries of the blocks.

8. The non-transitory computer-readable storage media of claim 1 , wherein transferring the blocks from the first cache to the second cache comprises:
moving the blocks from the first cache to the second cache, thereby invalidating the blocks in the first cache; and
updating the third directory to reflect the invalidated blocks.

9. The non-transitory computer-readable storage media of claim 1 , wherein transferring the blocks from the first cache to the second cache comprises transferring a portion of the blocks that are most recently used from the first cache to the second cache.

10. The non-transitory computer-readable storage media of claim 1 , wherein transferring the blocks from the first cache to the second cache comprises transferring the blocks in an order from most recently used blocks to least recently used blocks.

11. A multicore processor, comprising:
a first tile comprising a first core, a first cache, and a first directory that maps a first set of block addresses, wherein the first directory is a first component of a main memory coupled to the multicore processor, that main memory including a shared memory architecture, and the main memory is configured to operate with a directory based coherence protocol;
a second tile comprising a second core, a second cache, and a second directory that maps a second set of block addresses, wherein the second directory is a second component of the main memory coupled to the multicore processor;
a third tile comprising a third core, a third cache, and a third directory that maps a third set of block addresses, wherein the third directory is a third component of the main memory coupled to the multicore processor; and
wherein the multicore processor is configured to:
initiate migration of a thread executing on the first core from the first tile to the second tile;
determine block addresses of blocks to be transferred from the first cache to the second cache based on the migration of the thread executing on the first core from the first tile to the second core from the second tile in the multicore processor, wherein the block addresses of the blocks are determined by a scan of a cache tag array of the first cache;
identify that the third directory corresponds to the block addresses of the blocks to be transferred from the first cache to the second cache, wherein the third directory indicates that the first cache contains the blocks and the second cache does not share th

Assignees

• Solihin Yan
• Empire Technology Dev Llc

Inventors

• Solihin Yan

Classifications

• G06F9/4856

  resumption being on a different machine, e.g. task migration, virtual machine migration (G06F9/5088 takes precedence) · CPC title

• G06F12/0817 Primary

  using directory methods · CPC title

• G06F9/461 Primary

  Saving or restoring of program or task context · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F12/0806

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title