System and method for bank logical data remapping

Patent metadata

Field	Value
Publication number	US-9336129-B2
Application number	US-201314044548-A
Country	US
Kind code	B2
Filing date	Oct 2, 2013
Priority date	Oct 2, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A method and system are disclosed for remapping logical addresses between memory banks of discrete or embedded multi-bank storage device. The method may include a controller of a storage device tracking a total erase count for a storage device, determining if an erase count imbalance greater than a threshold exists between banks, and then remapping logical address ranges from the highest erase count bank to the lowest erase count bank to even out wear between the banks. The system may include a controller that may maintain a bank routing table, an erase counting mechanism and execute instructions for triggering a remapping process to remap an amount of logical addresses such that an address range is reduced for a hotter bank and increased for a colder bank.

First claim

What is claimed is:

1. A method of remapping storage of content between memory banks in a storage device, the method comprising:
in a storage device having a controller in communication with non-volatile memory, wherein the non-volatile memory comprises a plurality of memory banks and wherein each of the plurality of memory banks is associated with a respective unique range of logical block addresses, the controller:
detecting a bank remapping review event, wherein detecting the bank remapping review event comprises determining a total erase count for only multi-level cell (MLC) flash memory cells in the plurality of memory banks exceeds a predetermined storage device erase count;
in response to detecting the bank remapping review event, determining a difference in erase counts between a first memory bank having a highest erase count in the plurality of memory banks and a second memory bank having a lowest erase count in the plurality of memory banks; and
when the difference in erase counts exceeds a predetermined threshold, remapping logical block addresses from a first range of logical block addresses associated with the first memory bank to a second range of logical block addresses associated with the second memory bank.

2. The method of claim 1 , further comprising copying any valid data associated with the remapped logical block addresses from the first memory bank to the second memory bank.

3. A method of remapping storage of content between memory banks in a storage device, the method comprising:
in a storage device having a controller in communication with non-volatile memory, wherein the non-volatile memory comprises a plurality of memory banks and wherein each of the plurality of memory banks is associated with a respective unique range of logical block addresses, the controller:
detecting a bank remapping review event;
in response to detecting the bank remapping review event, determining a difference in erase counts between a first memory bank having a highest erase count in the plurality of memory banks and a second memory bank having a lowest erase count in the plurality of memory banks; and
when the difference in erase counts exceeds a predetermined threshold, remapping logical block addresses from a first range of logical block addresses associated with the first memory bank to a second range of logical block addresses associated with the second memory bank; and
wherein remapping logical block addresses comprises the controller of the storage device selecting a range of logical block addresses associated with the first memory bank and changing an association of the selected range of logical block addresses from the first memory bank to the second memory bank such that a total logical block address range associated with the first memory bank is reduced and a total logical block address range associated with the second memory bank is increased.

4. The method of claim 3 , wherein the controller first selects any logical block addresses from the first memory bank associated with logically erased data when selecting the range of logical block addresses, wherein logically erased data comprises data marked as obsolete prior to physical erase.

5. The method of claim 3 , wherein the controller selects logical block addresses for data most recently written to the first memory bank for the range of logical block addresses.

6. The method of claim 3 , wherein the controller selects logical block addresses associated with valid data and associates the selected logical block addresses to the second memory bank without copying the valid data from the first memory bank to the second memory bank, wherein the controller diverts data associated with the selected logical block addresses that is received in a subsequent host write command to the second memory bank.

7. The method of claim 3 , further comprising the controller updating an address table in the first memory bank to remove the range of logical block addresses, and updating an address table of the second memory bank to add the range of logical block addresses, wherein a total amount of used logical addresses associated with the first memory bank is reduced and a total amount of used logical block addresses associated with the second memory bank is increased.

8. The method of claim 1 , wherein the predetermined threshold between the highest erase count and the lowest erase count of the plurality of memory banks comprises at least a five percent difference between the highest erase count and the lowest erase count.

9. A storage device comprising:
a non-volatile memory having a plurality of memory banks and wherein each of the plurality of memory banks is associated with a respective unique range of logical block addresses; and
a controller in communication with the plurality of memory banks, the controller configured to:
detect a bank remapping review event, wherein the controller is configured to detect the bank remapping review event when a total erase count for only multi-level cell (MLC) flash memory cells in the plurality of memory banks exceeds a predetermined storage device erase count;
in response to detecting the bank remapping review event, determine a difference in erase counts between a first memory bank having a highest erase count in the plurality of memory banks and a second memory bank having a lowest erase count in the plurality of memory banks; and
when the difference between the highest and lowest erase counts exceeds a predetermined threshold:
remap logical block addresses from a first range of logical block addresses associated with the first memory bank to a second range of logical block addresses associated with the second memory bank.

10. The storage device of claim 9 , wherein the controller is further configured to copy any valid data associated with the remapped logical block addresses from the first memory bank to the second memory bank.

11. The storage device of claim 9 , wherein to remap logical block addresses the controller of the storage device is configured to select a range of logical block addresses associated with the first memory bank and change an association of the selected range of logical block addresses from the first memory bank to the second memory bank.

12. The storage device of claim 11 , wherein the controller is configured to first select any logical block addresses associated with trimmed data from the first memory bank when selecting the range of logical block addresses, wherein trimmed data comprises data marked as obsolete prior to erase.

13. The storage device of claim 11 , wherein the controller is configured to select logical block addresses for data most recently written to the first memory bank for the range of logical block addresses.

14. A storage device comprising:
a non-volatile memory having a plurality of memory banks and wherein each of the plurality of memory banks is associated with a respective unique range of logical block addresses; and
a controller in communication with the plurality of memory banks, the controller configured to:
detect a bank remapping review event;
in response to detecting the bank remapping review event, determine a difference in erase counts between a first memory bank having a highest erase count in the plurality of memory banks and a second memory bank having a lowest erase count in the plurality of memory banks; and
when the difference between the highest and lowest erase counts exceeds a predetermined threshold:
remap logical block addresses from a first range of logical block addresses associated with the first memory bank to a second range of logical block addresses associated

Assignees

• Bennett Alan
• Gorobets Sergey Anatolievich
• Sandisk Technologies Inc

Inventors

• Bennett Alan
• Gorobets Sergey Anatolievich

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F3/0649

  Lifecycle management · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F2212/7211

  Wear leveling · CPC title