Data structures for efficient tiled rendering

Patent metadata

Field	Value
Publication number	US-9336002-B2
Application number	US-201313967233-A
Country	US
Kind code	B2
Filing date	Aug 14, 2013
Priority date	Oct 26, 2012
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

One embodiment of the present invention includes a method for performing a multi-pass tiling test. The method includes combining a plurality of bounding boxes to generate a coarse bounding box. The method further includes identifying a first cache tile associated with a render surface and determining that the coarse bounding box intersects the first cache tile. The method further includes comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile. Finally, the method includes, for each bounding box included in the first set of one or more bounding boxes, processing one or more graphics primitives associated with the bounding box. One advantage of the disclosed technique is that the number of intersection calculations performed for each cache tile is reduced.

First claim

The invention claimed is:

1. A computer-implemented method for performing a multi-pass tiling test, the method comprising:
combining a plurality of bounding boxes to generate a coarse bounding box;
determining that the coarse bounding box intersects a first cache tile;
comparing each bounding box included in the plurality of bounding boxes against the first cache tile and identifying a first set of one or more bounding boxes included in the plurality of bounding boxes that intersects the first cache tile; and
for at least one bounding box included in the first set of one or more bounding boxes, processing one or more graphics primitives associated with the at least one bounding box.

2. The method of claim 1 , wherein processing the one or more graphics primitives associated with the at least one bounding box comprises:
generating a scissor rectangle based on the first cache tile; and
culling a first portion of the one or more graphics primitives based on the scissor rectangle.

3. The method of claim 2 , wherein processing the one or more graphics primitives associated with the at least one bounding box further comprises transmitting, based on the scissor rectangle, a second portion of the one or more graphics primitives to a screen space pipeline.

4. The method of claim 1 , wherein processing the one or more graphics primitives associated with the at least one bounding box comprises transmitting at least a portion of the one or more graphics primitives from a buffer to a screen space pipeline.

5. The method of claim 1 , wherein the coarse bounding box includes a plurality of indices, and each index is associated with a different bounding box included in the plurality of bounding boxes.

6. The method of claim 1 , wherein combining the plurality of bounding boxes to generate a coarse bounding box comprises accumulating bounding boxes until the coarse bounding box includes at least one of a threshold number of bounding boxes and a threshold number of primitives.

7. The method of claim 1 , further comprising:
determining that a second set of one or more bounding boxes included in the plurality of bounding boxes does not intersect the first cache tile; and
determining not to process the second set of one or more bounding boxes.

8. The method of claim 1 , further comprising:
determining that the coarse bounding box does not intersect a second cache tile; and
in response, not comparing each bounding box included in the plurality of bounding boxes against the second cache tile.

9. The method of claim 1 , wherein the one or more graphics primitives associated with the at least one bounding box included in the first set of one or more bounding boxes are stored in application programming interface (API) order.

10. The method of claim 1 , wherein at least one bounding box included in the plurality of bounding boxes comprises an accumulated bounding box that is associated with two or more graphics primitives.

11. A graphics processing pipeline, comprising:
a screen space pipeline; and
a tiling unit that:
combines a plurality of bounding boxes to generate a coarse bounding box;
identifies a first cache tile associated with a render surface;
determines that the coarse bounding box intersects the first cache tile;
compares each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile; and
for each bounding box included in the first set of one or more bounding boxes, processes one or more graphics primitives associated with the bounding box.

12. The graphics processing pipeline of claim 11 , wherein processing the one or more graphics primitives associated with the bounding box comprises:
generating a scissor rectangle based on the first cache tile; and
culling a first portion of the one or more graphics primitives based on the scissor rectangle.

13. The graphics processing pipeline of claim 12 , wherein processing the one or more graphics primitives associated with the bounding box further comprises transmitting, based on the scissor rectangle, a second portion of the one or more graphics primitives to the screen space pipeline.

14. The graphics processing pipeline of claim 11 , wherein processing the one or more graphics primitives associated with the bounding box comprises transmitting at least a portion of the one or more graphics primitives from a buffer to the screen space pipeline.

15. The graphics processing pipeline of claim 11 , wherein the coarse bounding box includes a plurality of indices, and each index is associated with a different bounding box included in the plurality of bounding boxes.

16. The graphics processing pipeline of claim 11 , wherein combining the plurality of bounding boxes to generate a coarse bounding box comprises accumulating bounding boxes until the coarse bounding box includes at least one of a threshold number of bounding boxes and a threshold number of primitives associated with the plurality of bounding boxes.

17. The graphics processing pipeline of claim 11 , wherein the tiling unit also:
determines that a second set of one or more bounding boxes included in the plurality of bounding boxes do not intersect the first cache tile; and
determines not to process the second set of one or more bounding boxes.

18. The graphics processing pipeline of claim 11 , wherein the tiling unit also:
identifies a second cache tile associated with the render surface;
determines that the coarse bounding box does not intersect the second cache tile; and
decides not to compare each bounding box included in the plurality of bounding boxes against the second cache tile.

19. The graphics processing pipeline of claim 11 , wherein at least one bounding box included in the plurality of bounding boxes comprises an accumulated bounding box that is associated with two or more graphics primitives.

20. A computing device, comprising:
a memory; and
a graphics processing pipeline that includes:
a screen space pipeline; and
a tiling unit that:
determines that a coarse bounding box intersects a first cache tile;
compares at least a first bounding box included in the coarse bounding box against the first cache tile to determine that the at least a first bounding box intersects the first cache tile; and
process one or more graphics primitives associated with the at least a first bounding box.

Assignees

• Nvidia Corp

Inventors

• Hakura Ziyad S
• Souillot Pierre
• Allison Cynthia
• Kirkland Dale L

Classifications

• G06F9/44

  Arrangements for executing specific programs · CPC title

• G06T17/20

  Finite element generation, e.g. wire-frame surface description, {tesselation} · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T15/80

  Shading · CPC title