Liquid crystal display device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9335600-B2
Application number	US-201213727166-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Jun 25, 2012
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

The present disclosure relates to a liquid crystal display device and a fabricating method thereof. The liquid crystal display device includes: first and second substrates bonded to each other; gate lines aligned on the first substrate; a data line and a common line on the first substrate; a large pixel electrode disposed at the intersecting point between the lines; a TFT at the intersecting point between the gate line and the data line; a protrusion pattern on the gate line; a passivation layer on the first substrate; branched common electrodes on the passivation layer; a pixel electrode connection pattern on the passivation layer; a black matrix and color filter layer on the second substrate; a column spacer on the second substrate; and a liquid crystal layer at between the substrates.

First claim

What is claimed is:

1. A liquid crystal display device comprising:
a first substrate and a second substrate bonded to each other with a spaced distance therebetween;
a plurality of gate lines aligned on the first substrate in one direction in parallel to each other;
a gate electrode extending from each of the gate lines;
a gate insulating layer formed on a surface of the substrate including the gate electrode;
a data line and a common line formed on the gate insulating layer to define pixel regions at intersecting points with the gate lines;
a pixel electrode disposed on each pixel region defined at the intersecting point between each gate line and the data line and the common line;
a transistor disposed at the intersecting point between each of the gate lines and the data line, the transistor having an active layer disposed on the gate electrode and the gate insulating layer, a source electrode, and a drain electrode spaced apart from the source electrode and having a first horizontal portion, a second horizontal portion, and a bent portion between the first and second horizontal portions;
a protrusion pattern formed on the gate line, and facing the second horizontal portion of the drain electrode in a direction parallel to the data line;
a passivation layer formed on a surface of the first substrate having the protrusion pattern, and exposing the pixel electrode;
a plurality of branched common electrodes formed on the passivation layer to be connected to the common line and overlap the pixel electrode;
a pixel electrode connection pattern formed on the passivation layer to connect the pixel electrode to the drain electrode via the exposed passivation layer;
a black matrix formed on the second substrate;
a color filter layer located between the black matrixes;
a column spacer formed on the second substrate corresponding to the protrusion pattern so as to be contactable with the protrusion pattern; and
a liquid crystal layer interposed between the first substrate and the second substrate,
wherein a distance between the second horizontal portion of the drain electrode and the protrusion pattern is longer than a distance between the first horizontal portion of the drain electrode and the protrusion pattern along the direction parallel to the data line.

2. The device of claim 1 , wherein the gate insulating layer is formed on an entire surface of the substrate including the gate electrode.

3. The device of claim 1 , wherein the transistor is a Thin Film Transistor.

4. The device of claim 1 , wherein the protrusion pattern is formed on the gate insulating layer located above the gate line adjacent to the drain electrode.

5. The device of any one of claim 1 , wherein the gate line has a perpendicular pattern overlapping the drain electrode to construct a parasitic capacitor.

6. A method for fabricating a liquid crystal display device comprising:
preparing a first substrate and a second substrate;
forming a plurality of gate lines aligned on the first substrate in one direction in parallel to each other, a gate electrode extending from each gate line, and a large pixel electrode;
forming a gate insulating layer on a surface of the substrate having the gate electrode;
forming a data line and a common line formed on the gate insulating layer to define pixel regions at intersecting points with the gate lines;
forming a transistor at the intersecting point between the gate line and the data line, the thin film transistor comprising an active layer on the gate insulating layer, a source electrode, and a drain electrode spaced apart from the source electrode and having a first horizontal portion, a second horizontal portion, and a bent portion between the first and second horizontal portions, and forming a protrusion pattern on the gate line to face the second horizontal portion of the drain electrode in a direction parallel to the data line;
forming a passivation layer formed on a surface of the first substrate having the protrusion pattern to expose the pixel electrode;
forming a plurality of branched common electrodes on the passivation layer, the branched common electrode being connected to the common line and overlapping the pixel electrode, and simultaneously forming a pixel electrode connection pattern on the passivation layer to connect the pixel electrode to the drain electrode;
forming a black matrix on the second substrate to define a non-pixel area;
forming a color filter layer on the second substrate corresponding to the pixel region between the black matrixes;
forming a column spacer on the second substrate corresponding to the protrusion pattern to be contactable with the protrusion pattern; and
forming a liquid crystal layer between the first substrate and the second substrate,
wherein a distance between the second horizontal portion of the drain electrode and the protrusion pattern is longer than a distance between the first horizontal portion of the drain electrode and the protrusion pattern along the direction parallel to the data line.

7. The method of claim 6 , wherein the gate insulating layer is formed on an entire surface of the substrate.

8. The method of claim 6 , wherein the transistor is a Thin Film Transistor.

9. The method of claim 6 , wherein the transistor and the protrusion pattern are simultaneously formed.

10. The method of claim 6 , wherein the protrusion pattern is formed on the gate insulating layer located above the gate line adjacent to the drain electrode.

11. The method of claim 6 , wherein the gate line has a perpendicular pattern overlapping the drain electrode to construct a parasitic capacitor.

12. The device of claim 5 , wherein the perpendicular pattern is parallel to the bent portion of the drain electrode.

13. The device of claim 5 , wherein the protrusion pattern is disposed between the perpendicular pattern of the gate line and the bent portion of the drain electrode.

Assignees

• Lg Display Co Ltd

Inventors

• Lee Byung-Hyun
• Lee Min-Jic

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10H20/855

  Optical field-shaping means, e.g. lenses · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title