Optical devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9335474-B2
Application number	US-201414311372-A
Country	US
Kind code	B2
Filing date	Jun 23, 2014
Priority date	Oct 13, 2009
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Provided is an optical device. The optical device includes a substrate having a waveguide region and a mounting region, a planar lightwave circuit (PLC) waveguide including a lower-clad layer and an upper-clad layer on the waveguide region of the substrate and a platform core between the lower-clad layer and the upper-clad layer, a terrace defined by etching the lower-clad layer on the mounting region of the substrate, the terrace including an interlocking part, an optical active chip mounted on the mounting region of the substrate, the optical active chip including a chip core therein, and a chip alignment mark disposed on a mounting surface of the optical active chip. The optical active chip is aligned by interlocking between the interlocking part of the terrace and the chip alignment mark of the optical active chip and mounted on the mounting region.

First claim

What is claimed is:

1. A method of fabricating an optical device, the method comprising:
sequentially forming a lower-clad layer, a platform core, and an upper-clad layer on both of a waveguide region of a substrate and a mounting region of the substrate;
performing a first etch process on a portion of the upper-clad layer, a portion of the platform core, and a portion of the lower-clad layer, which are each disposed on the mounting region of the substrate, to form a PLC waveguide in the waveguide region and adjust the portion of the lower-clad layer to have a first height in the mounting region;
performing a second etch process on the portion of the lower-clad layer having the first height disposed on the mounting region of the substrate to form a terrace having a trench and the first height, and adjust the portion of the lower-clad layer to have a second height;
forming a chip alignment mark on a mounting surface of an optical active chip comprising a chip core therein;
forming a solder film directly on the chip alignment mark;
after the forming the solder film, mounting the optical active chip on the mounting region of the substrate by aligning the optical active chip by interlocking between the trench of the terrace and the chip alignment mark of the optical active chip.

2. The method of claim 1 , further comprising:
forming a platform UBM on a part of the lower-clad layer having the second height and around the terrace, the platform UBM being disposed on the mounting region of the substrate; and
forming a chip UBM on the mounting surface of the optical active chip.

3. The method of claim 2 , wherein the chip UBM and the chip alignment mark are formed at the same time.

4. The method of claim 2 , further comprising forming another solder film on at least one of the platform UBM and the chip UBM.

5. The method of claim 4 , wherein the another solder film is formed on each of the platform UBM and the chip UBM.

6. The method of claim 1 , wherein the mounting includes positioning the chip alignment mark to protrude into the trench.

7. The method of claim 6 , wherein the mounting includes positioning the solder film to protrude from a bottom surface of the chip alignment mark so as to protrude farther into the trench than the chip alignment mark.

8. A method of fabricating an optical device, the method comprising:
sequentially forming a lower-clad layer, a platform core, and an upper-clad layer on both of a waveguide region of a substrate and a mounting region of the substrate;
performing a first etch process on a portion of the upper-clad layer, a portion of the platform core, and a portion of the lower-clad layer, which are each disposed on the mounting region of the substrate, to form a PLC waveguide in the waveguide region and adjust the portion of the lower-clad layer to have a first height in the mounting region;
performing a second etch process on the portion of the lower-clad layer having the first height disposed on the mounting region of the substrate to form a terrace having the first height and adjust the portion of the lower-clad layer to have a second height, the terrace being disposed on the mounting region of the substrate;
forming a platform alignment mark on an upper surface of the terrace disposed on the mounting region of the substrate, the platform alignment mark protruding from the upper surface of the terrace;
forming a chip alignment mark on a mounting surface of an optical active chip comprising a chip core therein; and
mounting the optical active chip on the mounting region of the substrate,
wherein the optical active chip is aligned by interlocking between the platform alignment mark on the terrace and the chip alignment mark of the optical active chip and mounted on the mounting region.

9. The method of claim 8 , wherein the platform alignment mark on the terrace and the chip alignment mark of the optical active chip have intaglio and relief shapes corresponding to each other, respectively.

10. The method of claim 8 , further comprising:
forming a platform UBM on a part of the portion of the lower-clad layer having the second height and around the terrace, the platform UBM being disposed on the mounting region of the substrate; and
forming a chip UBM on the mounting surface of the optical active chip.

11. The method of claim 10 , wherein the platform UBM and the platform alignment mark are formed at the same time.

12. The method of claim 10 , wherein the chip UBM and the chip alignment mark are formed at the same time.

13. The method of claim 10 , further comprising forming a solder film on at least one of the platform UBM and the chip UBM.

14. The method of claim 13 , wherein the solder film is formed on each of the platform UBM and the chip UBM.

15. The method of claim 8 , wherein the chip alignment mark protrudes from a bottom surface of the mounting surface of the optical active chip.

16. The method of claim 15 , wherein
the chip alignment mark includes chip alignment marks protruding from the mounting surface of the optical active chip, and
the platform alignment mark includes platform alignment marks,
the mounting comprises positioning the platform alignment marks to be disposed between the chip alignment marks so that the chip alignment marks are disposed within the platform alignment marks with a gap therebetween so as to be free of any contact with the platform alignment marks.

17. The method of claim 15 , wherein
the chip alignment mark includes chip alignment marks protruding from the mounting surface of the optical active chip, and
the mounting comprises positioning the platform alignment mark to be disposed between the chip alignment marks with a gap therebetween so as to be free of any contact with the chip alignment marks.

Assignees

• Korea Electronics Telecomm

Inventors

• Han Young-Tak
• Park Sang Ho
• Lee Dong-Hun
• Shin Jang Uk
• Han Sang-Pil
• Baek Yongsoon

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• G02B6/4231

  with intermediate elements, e.g. rods and balls, between the elements · CPC title

• G02B6/423 Primary

  using guiding surfaces for the alignment · CPC title

• G02B6/136 Primary

  by etching · CPC title

• G02B2006/12176

  Etching · CPC title