Network and method for implementing a high-availability grand master clock

US9331805B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9331805-B2
Application numberUS-201214115314-A
CountryUS
Kind codeB2
Filing dateMay 2, 2012
Priority dateMay 6, 2011
Publication dateMay 3, 2016
Grant dateMay 3, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In a network based on IEEE 1588, comprising a plurality of nodes ( 201, 501 ) and a plurality of connections where each connection connects at least two nodes to allow communication between nodes including the exchange of messages according to a network protocol, the synchronization of IEEE 1588 is improved by allowing multiple grandmaster clocks ( 701 ) to operate simultaneously in the system. Thus, the re-election protocol of IEEE 1588 is made obsolete. For this, a multitude of nodes form a subsystem implementing a high-availability grand master clock ( 301 ) according to the IEEE 1588 Standard, wherein the subsystem is configured to tolerate the failure of at least one of said nodes forming said subsystem. Bi-directional communication link ( 401 ) are configured for physically connecting a IEEE 1588 Master clocks ( 201 ) and/or IEEE 1588 Slave clocks ( 201 ) to the subsystem implementing a high-availability grand master clock ( 301 ).

First claim

Opening claim text (preview).

The invention claimed is: 1. A network comprising a plurality of nodes and a plurality of connections where each connection connects at least two nodes to allow communication between connected nodes including an exchange of messages according to a network protocol comprising: a high-availability grand master clock according to the IEEE 1588 Standard that is implemented by a subsystem of the network of at least two computing nodes that includes a switch and is configured to tolerate failure of at least one of at least two nodes in the subsystem, where the high-availability grand master clock provides a compression function that configures the subsystem to: receive IEEE Sync messages from a plurality of standard IEEE 1588 grand master clocks connected to the subsystem implementing the high-availability grandmaster clock, generate a new IEEE 1588 Sync message based upon the IEEE 1588 Sync messages received from the plurality of standard IEEE 1588 grandmaster clocks, and transmit the new IEEE Sync message over at least one bi-directional communication link to at least one of an IEEE 1588 Master clock and IEEE 1588 Slave clock, where each at least one bi-directional communication link physically connects one of an IEEE 1588 Master clock and an IEEE 1588 Slave clock to the subsystem implementing the high-availability grand master clock. 2. The network according to claim 1 , characterized in that the high-availability grand master clock is configured to generate and send IEEE 1588 Announce messages that guarantee that the high-availability grand master clock is selected as the best master by an IEEE 1588 best master clock algorithm. 3. The network according to claim 2 , characterized in that the high-availability grand master clock is configured to not forward at least one of IEEE 1588 Sync messages and the IEEE 1588 Announce messages to the the plurality of standard IEEE 1588 grand master clocks. 4. The network according to claim 1 , wherein the high-availability grand master clock consumes the IEEE 1588 Sync messages and IEEE 1588 Announce messages from the plurality of standard IEEE 1588 grand master clocks and does not forward the received IEEE 1588 Sync messages, and timing information represented by the IEEE 1588 Sync messages generated by the high-availability grand master clock represents at least one of a mean, a median, a fault-tolerant mean, and a fault-tolerant median value of the timing information of the IEEE 1588 Sync messages received from the plurality of standard IEEE 1588 grand master clocks. 5. The network according to claim 4 wherein the representation of at least one of a mean, a median, a fault-tolerant mean, and a fault-tolerant median value of the timing information of the IEEE 1588 Sync messages received from standard IEEE 1588 grand master clocks by the new IEEE 1588 Sync messages generated by the high-availability grand master clock is an offset value. 6. The network according to claim 1 , characterized in that the subsystem is realized as a TTEthernet system configured to realize the high-availability grand master clock, where the TTEthernet system includes at least one network interface card and at least one switch and wherein each of the at least one network interface cards is connected to at least one switch by a bi-directional communication link. 7. The network according to claim 6 , in which the TTEthernet system implements at least one IEEE 1588 grand master clock. 8. The network according to claim 6 , where the network is connected to a plurality standard IEEE 1588 grand master clocks, wherein the TTEthernet system is configured to generate an IEEE 1588 Sync message as a response to receiving an IEEE 1588 Sync message from one of the plurality of standard IEEE 1588 grand master clocks , wherein each non-faulty one of the plurality of standard IEEE 1588 grand master clock generates an IEEE 1588 Sync message at the same point in time according a local perception of time of each non-faulty redundant standard IEEE 1588 grand master clock , and wherein the compression function of the high-availability grand master clock is a TTEthernet compression function that is used to collect the IEEE 1588 Sync messages from each of the plurality of standard IEEE 1588 grand master clocks clock and to generate a new IEEE 1588 Sync message. 9. The network according to claim 8 , in which the TTEthernet compression function is implemented in the at least one switch. 10. The network according to claim 8 , wherein a plurality of TTEthernet compression functions is implemented in the at least one switch. 11. The network according to claim 10 , the plurality of standard IEEE 1588 grand master clocks are configured to send IEEE 1588 Sync messages to each of the plurality of TTEthernet compression functions and each of the plurality of TTEthernet compression functions generates new IEEE 1588 Sync messages. 12. The network according to claim 1 wherein one of a standard IEEE 1588 master clock and a standard IEEE 1588 slave clock is configured to receive redundant IEEE 1588 Sync messages as produced by the high-availability grand master clock, whereby the one of the IEEE 1588 master clock and the IEEE 1588 slave clock uses at least one of a mean, a median, a fault-tolerant mean, a fault-tolerant median of the timing information carried by the redundant IEEE 1588 Sync messages from the high-availability grand master clock to correct a local clock. 13. A method for implementing a network comprising: providing a plurality of computing nodes forming a subsystem; implementing a high-availability grand master clock according to the IEEE 1588 Standard using the subsystem; that tolerates a failure of at least one of the plurality of nodes forming the subsystem by providing a compression function configured to: receive IEEE Sync messages from a plurality of standard IEEE 1588 grand master clocks connected to the subsystem implementing the high-availability grandmaster clock, generate a new IEEE 1588 Sync message based upon the IEEE 1588 Sync messages received from the plurality of standard IEEE 1588 grandmaster clocks, and transmit the new IEEE Sync message over at least one bi-directional communication link to at least one of an IEEE 1588 Master clock and IEEE 1588 Slave clock, where bi-directional link physically connects at least two IEEE clocks that are each one of an IEEE 1588 Master clock and IEEE 1588 Slave clock to the subsystem implementing a high-availability grand master clock . 14. A TTEthernet (Time-Triggered Ethernet) switch configured in a subsystem of a plurality of nodes in a network that provides an IEEE 1588 high-availability grand master clock, the TTEthernet switch comprising: a network interface card; at least one switch wherein each of the at least network interface cards is connected to at least one switch by a bi-directional communication link; and where the network is connected to a plurality of standard IEEE 1588 grand master clocks , wherein the TTEthernet switch is configured to receive IEEE Sync messages from the plurality of standard IEEE 1588 grand master clocks connected to the subsystem implementing the high availability grandmaster clock, generate a new IEEE 1588 Sync message based on the IEEE 1588 Sync messages from the plurality of standard IEEE 1588 grand master clocks, and transmit the new IEEE Sync message over at least one bi-directional communication link to at least one of an IEEE 1588 Master clock and IEEE 1588 Slave clock, where bi-directional link physically connects the one of an IEEE 1588 Master clock and IEEE 1588 Slave clock to the subsystem implementing a high-availability grand master clock and wh

Assignees

Inventors

Classifications

  • H04J3/0658Primary

    Clock or time synchronisation among packet nodes · CPC title

  • H04J3/0641Primary

    Change of the master or reference, e.g. take-over or failure of the master · CPC title

  • Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

  • Mutual · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9331805B2 cover?
In a network based on IEEE 1588, comprising a plurality of nodes ( 201, 501 ) and a plurality of connections where each connection connects at least two nodes to allow communication between nodes including the exchange of messages according to a network protocol, the synchronization of IEEE 1588 is improved by allowing multiple grandmaster clocks ( 701 ) to operate simultaneously in the system.…
Who is the assignee on this patent?
Steiner Wilfried, Bauer Günther, Schwarz Martin, and 1 more
What technology area does this patent fall under?
Primary CPC classification H04J3/0658. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 03 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).