Apparatus and method for generating an oscillating output signal

Patent metadata

Field	Value
Publication number	US-9331704-B2
Application number	US-201313757666-A
Country	US
Kind code	B2
Filing date	Feb 1, 2013
Priority date	Feb 1, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

An apparatus for generating an oscillating output signal includes an inductive-capacitive (LC) circuit and a current tuning circuit. The LC circuit includes a primary inductor and a varactor coupled to the primary inductor. A capacitance of the varactor is responsive to a voltage at a control input of the varactor. The current tuning circuit includes a secondary inductor and a current driving circuit coupled to the secondary inductor. The current driving circuit is responsive to a current at a control input of the current driving circuit. An effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor.

First claim

What is claimed is:

1. A method of generating an oscillating output signal, the method comprising:
providing a tuning current to a first input of an oscillator having a primary inductor that is inductively coupled with a secondary inductor, wherein the oscillator is configured to generate the oscillating output signal, and wherein the tuning current is provided to the secondary inductor through one or more transconductors;
providing a tuning voltage to a second input of the oscillator;
wherein a frequency of the oscillator is independently responsive to the tuning current and to the tuning voltage;
applying a phase shift to the oscillating output signal, wherein the phase-shifted oscillating output signal is configured to control the one or more transconductors such that a phase of a current flow through the secondary inductor is aligned with a phase of a current flow through the primary inductor, wherein applying the phase shift is performed via a phase shifter comprising:
a p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a power supply voltage;
an n-channel metal oxide semiconductor (NMOS) transistor having a source coupled to a reference potential, wherein:
a gate of the PMOS transistor is coupled to a gate of the NMOS transistor; and
a drain of the PMOS transistor is coupled to a drain of the NMOS transistor and a gate of one of the transconductors;

a resistor coupled between the gate of the PMOS transistor and the drain of the PMOS transistor; and
a capacitor coupled between an output of the oscillator and the gate of the PMOS transistor; and

selectively shunting the phase-shifted oscillating output signal to the reference potential via one or more capacitors, wherein the oscillator is included in a phase-locked loop (PLL), wherein a phase modulated signal is generated at an output of the oscillator based on two point modulation (TPM) inputs, and wherein the TPM inputs include a high pass modulation data input and a low pass modulation data input, wherein the tuning current corresponds to the high pass modulation data input and wherein the tuning current is generated by a digital-to-analog converter (DAC) external to the PLL, and wherein the tuning current is responsive to phase modulation data provided to the DAC.

2. The method of claim 1 , wherein the oscillator is a hybrid voltage and current controlled oscillator.

3. The method of claim 1 , wherein the second input is coupled to provide the tuning voltage to a variable capacitance element of the oscillator.

4. The method of claim 1 , wherein the tuning current corresponds to phase modulation data and wherein the tuning voltage corresponds to a center frequency of the oscillator.

5. The method of claim 1 , wherein the tuning voltage is generated within the PLL.

6. The method of claim 1 , wherein the DAC is within a baseband processor, wherein the PLL is within a radio frequency integrated circuit (RFIC), and wherein the tuning current is provided to the first input of the oscillator via a transmitter quadrature baseband input pin.

7. The method of claim 1 , wherein the low pass modulation data is provided via a single data pin.

8. The method of claim 1 , wherein a high-pass modulation circuit provides the phase modulation data to the DAC.

9. The method of claim 8 , wherein the tuning current adjusts a phase of the oscillator while the PLL is frequency locked.

10. The method of claim 9 , wherein the tuning voltage is configured to regulate a center frequency of the oscillator while the phase of the oscillator is adjusted.

11. The method of claim 10 , wherein regulating the center frequency of the oscillator includes maintaining the center frequency at a substantially constant frequency.

12. The method of claim 1 , wherein the first input is coupled to provide the tuning current across the secondary inductor within the oscillator, wherein the tuning current across the secondary inductor inductively couples with a current across the primary inductor within the oscillator to change an effective inductance of the primary inductor, and wherein the second input is coupled to provide the tuning voltage to a variable capacitor that is coupled to the primary inductor.

13. The method of claim 12 , wherein the frequency of the oscillator is adjusted when the effective inductance of the primary inductor is changed.

14. The method of claim 12 , wherein a phase of the oscillator is adjusted when the effective inductance of the primary inductor is changed.

15. An apparatus for generating an oscillating output signal, the apparatus comprising:
an inductive-capacitive (LC) circuit included in an oscillator comprising:
a primary inductor; and
a varactor coupled to the primary inductor, wherein a capacitance of the varactor is responsive to a voltage at a control input of the varactor;

a current tuning circuit comprising:
a secondary inductor; and
a current driving circuit coupled to the secondary inductor and responsive to a current at a control input of the current driving circuit,

wherein an effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and
wherein a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor;
a phase shifter connected to an output of the oscillator, wherein the phase shifter aligns a phase of a current flow through the primary inductor and a phase of a current flow through the secondary inductor, wherein the phase shifter comprises:
a p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a power supply voltage;
an n-channel metal oxide semiconductor (NMOS) transistor having a source coupled to a reference potential, wherein:
a gate of the PMOS transistor is coupled to a gate of the NMOS transistor; and
a drain of the PMOS transistor is coupled to a drain of the NMOS transistor and a gate of one of the transconductors;

a resistor coupled between the gate of the PMOS transistor and the drain of the PMOS transistor; and
a capacitor coupled between an output of the oscillator and the gate of the PMOS transistor; and

one or more switches configured to selectively shunt an output of the phase shifter to the reference potential via one or more capacitors, wherein the oscillator is included in a phase-locked loop (PLL), wherein a phase modulated signal is generated at an output of the oscillator based on two point modulation (TPM) inputs, and wherein the TPM inputs include a high pass modulation data input and a low pass modulation data input, wherein the tuning current corresponds to the high pass modulation data input and wherein the tuning current is generated by a digital-to-analog converter (DAC) external to the PLL, and wherein the tuning current is responsive to phase modulation data provided to the DAC.

16. The apparatus of claim 15 , wherein the control input of the current driving circuit is coupled to a baseband processor via a first single analog pin.

17. The apparatus of claim 15 , further comprising:
the PLL, wherein the LC circuit and the current tuning circuit are included within the oscillator of the PLL and wherein the PLL is coupled to provide the voltage to the control input of the varactor.

18. The apparatus of claim 17 , wherein the PLL further includes a divider circuit and wherein a control input of the divider circuit is coupled to a low pass modulation circuit of a baseband processor.

19. The apparatus of claim 18 , wh

Assignees

• Qualcomm Inc

Inventors

• Tang Yiwu
• Hu Jianyun
• Narathong Chiewcharn

Classifications

• H03L7/16 Primary

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03B2201/0208

  the means being an element with a variable capacitance, e.g. capacitance diode · CPC title

• H03B2201/0216

  the means being an element with a variable inductance · CPC title

• H03L7/104

  using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence) · CPC title

• H03B5/1215

  the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair · CPC title